1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 3 4 ; SI-LABEL: {{^}}br_i1_phi: 5 ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} 6 ; SI: s_and_saveexec_b64 7 ; SI: v_mov_b32_e32 [[REG]], -1{{$}} 8 ; SI: v_cmp_ne_u32_e32 vcc, 0, [[REG]] 9 ; SI: s_and_saveexec_b64 10 ; SI: s_endpgm 11 define amdgpu_kernel void @br_i1_phi(i32 %arg) { 12 bb: 13 %tidig = call i32 @llvm.amdgcn.workitem.id.x() 14 %cmp = trunc i32 %tidig to i1 15 br i1 %cmp, label %bb2, label %bb3 16 17 bb2: ; preds = %bb 18 br label %bb3 19 20 bb3: ; preds = %bb2, %bb 21 %tmp = phi i1 [ true, %bb2 ], [ false, %bb ] 22 br i1 %tmp, label %bb4, label %bb6 23 24 bb4: ; preds = %bb3 25 %val = load volatile i32, i32 addrspace(1)* undef 26 %tmp5 = mul i32 %val, %arg 27 br label %bb6 28 29 bb6: ; preds = %bb4, %bb3 30 ret void 31 } 32 33 declare i32 @llvm.amdgcn.workitem.id.x() #0 34 35 attributes #0 = { nounwind readnone } 36
