1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s 2 3 target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" 4 target triple = "amdgcn--amdpal" 5 6 ; The first image store and the second image load use the same descriptor and 7 ; the same coordinate. Check that they do not get swapped by the machine 8 ; instruction scheduler. 9 10 ; GCN-LABEL: {{^}}_amdgpu_cs_main: 11 ; GCN: image_load 12 ; GCN: image_store 13 ; GCN: image_load 14 ; GCN: image_store 15 16 define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <3 x i32> inreg %arg3, i32 inreg %arg4, <3 x i32> %arg5) local_unnamed_addr #0 { 17 .entry: 18 %tmp = call i64 @llvm.amdgcn.s.getpc() #1 19 %tmp6 = bitcast i64 %tmp to <2 x i32> 20 %.0.vec.insert = insertelement <2 x i32> undef, i32 %arg2, i32 0 21 %.4.vec.insert = shufflevector <2 x i32> %.0.vec.insert, <2 x i32> %tmp6, <2 x i32> <i32 0, i32 3> 22 %tmp7 = bitcast <2 x i32> %.4.vec.insert to i64 23 %tmp8 = inttoptr i64 %tmp7 to [4294967295 x i8] addrspace(4)* 24 %tmp9 = add <3 x i32> %arg3, %arg5 25 %tmp10 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(4)* %tmp8, i64 0, i64 32 26 %tmp11 = bitcast i8 addrspace(4)* %tmp10 to <8 x i32> addrspace(4)*, !amdgpu.uniform !0 27 %tmp12 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp11, align 16 28 %tmp13.0 = extractelement <3 x i32> %tmp9, i32 0 29 %tmp13.1 = extractelement <3 x i32> %tmp9, i32 1 30 %tmp14 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp12, i32 0, i32 0) #0 31 %tmp15 = inttoptr i64 %tmp7 to <8 x i32> addrspace(4)* 32 %tmp16 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp15, align 16 33 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %tmp14, i32 15, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp16, i32 0, i32 0) #0 34 %tmp17 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp15, align 16 35 %tmp18 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 165, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp17, i32 0, i32 0) #0 36 %tmp19 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(4)* %tmp8, i64 0, i64 64 37 %tmp20 = bitcast i8 addrspace(4)* %tmp19 to <8 x i32> addrspace(4)*, !amdgpu.uniform !0 38 %tmp21 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp20, align 16 39 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %tmp18, i32 15, i32 %tmp13.0, i32 %tmp13.1, <8 x i32> %tmp21, i32 0, i32 0) #0 40 ret void 41 } 42 43 ; Function Attrs: nounwind readnone speculatable 44 declare i64 @llvm.amdgcn.s.getpc() #1 45 46 ; Function Attrs: nounwind readonly 47 declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #2 48 49 ; Function Attrs: nounwind writeonly 50 declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32, i32, i32, <8 x i32>, i32, i32) #3 51 52 attributes #0 = { nounwind } 53 attributes #1 = { nounwind readnone speculatable } 54 attributes #2 = { nounwind readonly } 55 attributes #3 = { nounwind writeonly } 56 57 !0 = !{} 58
