1 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN 2 # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI 3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI 4 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI,GFX9 5 6 --- | 7 define amdgpu_kernel void @div_fmas() { ret void } 8 define amdgpu_kernel void @s_getreg() { ret void } 9 define amdgpu_kernel void @s_setreg() { ret void } 10 define amdgpu_kernel void @vmem_gt_8dw_store() { ret void } 11 define amdgpu_kernel void @readwrite_lane() { ret void } 12 define amdgpu_kernel void @rfe() { ret void } 13 define amdgpu_kernel void @s_mov_fed_b32() { ret void } 14 define amdgpu_kernel void @s_movrel() { ret void } 15 define amdgpu_kernel void @v_interp() { ret void } 16 define amdgpu_kernel void @dpp() { ret void } 17 18 define amdgpu_kernel void @mov_fed_hazard_crash_on_dbg_value(i32 addrspace(1)* %A) { 19 entry: 20 %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) 21 store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 22 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !5, metadata !11), !dbg !12 23 ret void 24 } 25 26 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 27 28 !llvm.dbg.cu = !{!0} 29 !llvm.module.flags = !{!3, !4} 30 31 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (trunk 268929)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) 32 !1 = !DIFile(filename: "test01.cl", directory: "/dev/null") 33 !2 = !{} 34 !3 = !{i32 2, !"Dwarf Version", i32 2} 35 !4 = !{i32 2, !"Debug Info Version", i32 3} 36 !5 = !DILocalVariable(name: "A", arg: 1, scope: !6, file: !1, line: 1, type: !9) 37 !6 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2) 38 !7 = !DISubroutineType(types: !8) 39 !8 = !{null, !9} 40 !9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, align: 32) 41 !10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) 42 !11 = !DIExpression() 43 !12 = !DILocation(line: 1, column: 30, scope: !6) 44 45 ... 46 --- 47 # GCN-LABEL: name: div_fmas 48 49 # GCN-LABEL: bb.0: 50 # GCN: S_MOV_B64 51 # GCN-NOT: S_NOP 52 # GCN: V_DIV_FMAS 53 54 # GCN-LABEL: bb.1: 55 # GCN: V_CMP_EQ_I32 56 # GCN: S_NOP 57 # GCN: S_NOP 58 # GCN: S_NOP 59 # GCN: S_NOP 60 # GCN: V_DIV_FMAS_F32 61 62 # GCN-LABEL: bb.2: 63 # GCN: V_CMP_EQ_I32 64 # GCN: S_NOP 65 # GCN: S_NOP 66 # GCN: S_NOP 67 # GCN: S_NOP 68 # GCN: V_DIV_FMAS_F32 69 70 # GCN-LABEL: bb.3: 71 # GCN: V_DIV_SCALE_F32 72 # GCN: S_NOP 73 # GCN: S_NOP 74 # GCN: S_NOP 75 # GCN: S_NOP 76 # GCN: V_DIV_FMAS_F32 77 name: div_fmas 78 79 body: | 80 bb.0: 81 $vcc = S_MOV_B64 0 82 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec 83 S_BRANCH %bb.1 84 85 bb.1: 86 implicit $vcc = V_CMP_EQ_I32_e32 $vgpr1, $vgpr2, implicit $exec 87 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec 88 S_BRANCH %bb.2 89 90 bb.2: 91 $vcc = V_CMP_EQ_I32_e64 $vgpr1, $vgpr2, implicit $exec 92 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec 93 S_BRANCH %bb.3 94 95 bb.3: 96 $vgpr4, $vcc = V_DIV_SCALE_F32 $vgpr1, $vgpr1, $vgpr3, implicit $exec 97 $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec 98 S_ENDPGM 99 100 ... 101 102 ... 103 --- 104 # GCN-LABEL: name: s_getreg 105 106 # GCN-LABEL: bb.0: 107 # GCN: S_SETREG 108 # GCN: S_NOP 0 109 # GCN: S_NOP 0 110 # GCN: S_GETREG 111 112 # GCN-LABEL: bb.1: 113 # GCN: S_SETREG_IMM32 114 # GCN: S_NOP 0 115 # GCN: S_NOP 0 116 # GCN: S_GETREG 117 118 # GCN-LABEL: bb.2: 119 # GCN: S_SETREG 120 # GCN: S_NOP 0 121 # GCN: S_GETREG 122 123 # GCN-LABEL: bb.3: 124 # GCN: S_SETREG 125 # GCN-NEXT: S_GETREG 126 127 name: s_getreg 128 129 body: | 130 bb.0: 131 S_SETREG_B32 $sgpr0, 1 132 $sgpr1 = S_GETREG_B32 1 133 S_BRANCH %bb.1 134 135 bb.1: 136 S_SETREG_IMM32_B32 0, 1 137 $sgpr1 = S_GETREG_B32 1 138 S_BRANCH %bb.2 139 140 bb.2: 141 S_SETREG_B32 $sgpr0, 1 142 $sgpr1 = S_MOV_B32 0 143 $sgpr2 = S_GETREG_B32 1 144 S_BRANCH %bb.3 145 146 bb.3: 147 S_SETREG_B32 $sgpr0, 0 148 $sgpr1 = S_GETREG_B32 1 149 S_ENDPGM 150 ... 151 152 ... 153 --- 154 # GCN-LABEL: name: s_setreg 155 156 # GCN-LABEL: bb.0: 157 # GCN: S_SETREG 158 # GCN: S_NOP 0 159 # VI: S_NOP 0 160 # GCN-NEXT: S_SETREG 161 162 # GCN-LABEL: bb.1: 163 # GCN: S_SETREG 164 # GCN: S_NOP 0 165 # VI: S_NOP 0 166 # GCN-NEXT: S_SETREG 167 168 # GCN-LABEL: bb.2: 169 # GCN: S_SETREG 170 # GCN-NEXT: S_SETREG 171 172 name: s_setreg 173 174 body: | 175 bb.0: 176 S_SETREG_B32 $sgpr0, 1 177 S_SETREG_B32 $sgpr1, 1 178 S_BRANCH %bb.1 179 180 bb.1: 181 S_SETREG_B32 $sgpr0, 64 182 S_SETREG_B32 $sgpr1, 128 183 S_BRANCH %bb.2 184 185 bb.2: 186 S_SETREG_B32 $sgpr0, 1 187 S_SETREG_B32 $sgpr1, 0 188 S_ENDPGM 189 ... 190 191 ... 192 --- 193 # GCN-LABEL: name: vmem_gt_8dw_store 194 195 # GCN-LABEL: bb.0: 196 # GCN: BUFFER_STORE_DWORD_OFFSET 197 # GCN-NEXT: V_MOV_B32 198 # GCN: BUFFER_STORE_DWORDX3_OFFSET 199 # CIVI: S_NOP 200 # GCN-NEXT: V_MOV_B32 201 # GCN: BUFFER_STORE_DWORDX4_OFFSET 202 # GCN-NEXT: V_MOV_B32 203 # GCN: BUFFER_STORE_DWORDX4_OFFSET 204 # CIVI: S_NOP 205 # GCN-NEXT: V_MOV_B32 206 # GCN: BUFFER_STORE_FORMAT_XYZ_OFFSET 207 # CIVI: S_NOP 208 # GCN-NEXT: V_MOV_B32 209 # GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET 210 # CIVI: S_NOP 211 # GCN-NEXT: V_MOV_B32 212 213 # GCN-LABEL: bb.1: 214 # GCN: FLAT_STORE_DWORDX2 215 # GCN-NEXT: V_MOV_B32 216 # GCN: FLAT_STORE_DWORDX3 217 # CIVI: S_NOP 218 # GCN-NEXT: V_MOV_B32 219 # GCN: FLAT_STORE_DWORDX4 220 # CIVI: S_NOP 221 # GCN-NEXT: V_MOV_B32 222 # GCN: FLAT_ATOMIC_CMPSWAP_X2 223 # CIVI: S_NOP 224 # GCN-NEXT: V_MOV_B32 225 # GCN: FLAT_ATOMIC_FCMPSWAP_X2 226 # CIVI: S_NOP 227 # GCN: V_MOV_B32 228 229 name: vmem_gt_8dw_store 230 231 body: | 232 bb.0: 233 BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec 234 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 235 BUFFER_STORE_DWORDX3_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec 236 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 237 BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec 238 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 239 BUFFER_STORE_DWORDX4_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec 240 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 241 BUFFER_STORE_FORMAT_XYZ_OFFSET $vgpr2_vgpr3_vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec 242 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 243 BUFFER_STORE_FORMAT_XYZW_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec 244 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 245 BUFFER_ATOMIC_CMPSWAP_X2_OFFSET $vgpr2_vgpr3_vgpr4_vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, implicit $exec 246 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 247 S_BRANCH %bb.1 248 249 bb.1: 250 FLAT_STORE_DWORDX2 $vgpr0_vgpr1, $vgpr2_vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr 251 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 252 FLAT_STORE_DWORDX3 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit $exec, implicit $flat_scr 253 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 254 FLAT_STORE_DWORDX4 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit $exec, implicit $flat_scr 255 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 256 FLAT_ATOMIC_CMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr 257 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 258 FLAT_ATOMIC_FCMPSWAP_X2 $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit $exec, implicit $flat_scr 259 $vgpr3 = V_MOV_B32_e32 0, implicit $exec 260 S_ENDPGM 261 262 ... 263 264 ... 265 --- 266 267 # GCN-LABEL: name: readwrite_lane 268 269 # GCN-LABEL: bb.0: 270 # GCN: V_ADD_I32 271 # GCN: S_NOP 272 # GCN: S_NOP 273 # GCN: S_NOP 274 # GCN: S_NOP 275 # GCN: V_READLANE_B32 276 277 # GCN-LABEL: bb.1: 278 # GCN: V_ADD_I32 279 # GCN: S_NOP 280 # GCN: S_NOP 281 # GCN: S_NOP 282 # GCN: S_NOP 283 # GCN: V_WRITELANE_B32 284 285 # GCN-LABEL: bb.2: 286 # GCN: V_ADD_I32 287 # GCN: S_NOP 288 # GCN: S_NOP 289 # GCN: S_NOP 290 # GCN: S_NOP 291 # GCN: V_READLANE_B32 292 293 # GCN-LABEL: bb.3: 294 # GCN: V_ADD_I32 295 # GCN: S_NOP 296 # GCN: S_NOP 297 # GCN: S_NOP 298 # GCN: S_NOP 299 # GCN: V_WRITELANE_B32 300 301 name: readwrite_lane 302 303 body: | 304 bb.0: 305 $vgpr0,$sgpr0_sgpr1 = V_ADD_I32_e64 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 306 $sgpr4 = V_READLANE_B32 $vgpr4, $sgpr0 307 S_BRANCH %bb.1 308 309 bb.1: 310 $vgpr0,$sgpr0_sgpr1 = V_ADD_I32_e64 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 311 $vgpr4 = V_WRITELANE_B32 $sgpr0, $sgpr0, $vgpr4 312 S_BRANCH %bb.2 313 314 bb.2: 315 $vgpr0,implicit $vcc = V_ADD_I32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 316 $sgpr4 = V_READLANE_B32 $vgpr4, $vcc_lo 317 S_BRANCH %bb.3 318 319 bb.3: 320 $vgpr0,implicit $vcc = V_ADD_I32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec 321 $vgpr4 = V_WRITELANE_B32 $sgpr4, $vcc_lo, $vgpr4 322 S_ENDPGM 323 324 ... 325 326 ... 327 --- 328 329 # GCN-LABEL: name: rfe 330 331 # GCN-LABEL: bb.0: 332 # GCN: S_SETREG 333 # VI: S_NOP 334 # GCN-NEXT: S_RFE_B64 335 336 # GCN-LABEL: bb.1: 337 # GCN: S_SETREG 338 # GCN-NEXT: S_RFE_B64 339 340 name: rfe 341 342 body: | 343 bb.0: 344 S_SETREG_B32 $sgpr0, 3 345 S_RFE_B64 $sgpr2_sgpr3 346 S_BRANCH %bb.1 347 348 bb.1: 349 S_SETREG_B32 $sgpr0, 0 350 S_RFE_B64 $sgpr2_sgpr3 351 S_ENDPGM 352 353 ... 354 355 ... 356 --- 357 358 # GCN-LABEL: name: s_mov_fed_b32 359 360 # GCN-LABEL: bb.0: 361 # GCN: S_MOV_FED_B32 362 # GFX9: S_NOP 363 # GCN-NEXT: S_MOV_B32 364 365 # GCN-LABEL: bb.1: 366 # GCN: S_MOV_FED_B32 367 # GFX9: S_NOP 368 # GCN-NEXT: V_MOV_B32 369 name: s_mov_fed_b32 370 371 body: | 372 bb.0: 373 $sgpr0 = S_MOV_FED_B32 $sgpr0 374 $sgpr0 = S_MOV_B32 $sgpr0 375 S_BRANCH %bb.1 376 377 bb.1: 378 $sgpr0 = S_MOV_FED_B32 $sgpr0 379 $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec 380 S_ENDPGM 381 382 ... 383 384 ... 385 --- 386 387 # GCN-LABEL: name: s_movrel 388 389 # GCN-LABEL: bb.0: 390 # GCN: S_MOV_B32 391 # GFX9: S_NOP 392 # GCN-NEXT: S_MOVRELS_B32 393 394 # GCN-LABEL: bb.1: 395 # GCN: S_MOV_B32 396 # GFX9: S_NOP 397 # GCN-NEXT: S_MOVRELS_B64 398 399 # GCN-LABEL: bb.2: 400 # GCN: S_MOV_B32 401 # GFX9: S_NOP 402 # GCN-NEXT: S_MOVRELD_B32 403 404 # GCN-LABEL: bb.3: 405 # GCN: S_MOV_B32 406 # GFX9: S_NOP 407 # GCN-NEXT: S_MOVRELD_B64 408 409 name: s_movrel 410 411 body: | 412 bb.0: 413 $m0 = S_MOV_B32 0 414 $sgpr0 = S_MOVRELS_B32 $sgpr0, implicit $m0 415 S_BRANCH %bb.1 416 417 bb.1: 418 $m0 = S_MOV_B32 0 419 $sgpr0_sgpr1 = S_MOVRELS_B64 $sgpr0_sgpr1, implicit $m0 420 S_BRANCH %bb.2 421 422 bb.2: 423 $m0 = S_MOV_B32 0 424 $sgpr0 = S_MOVRELD_B32 $sgpr0, implicit $m0 425 S_BRANCH %bb.3 426 427 bb.3: 428 $m0 = S_MOV_B32 0 429 $sgpr0_sgpr1 = S_MOVRELD_B64 $sgpr0_sgpr1, implicit $m0 430 S_ENDPGM 431 ... 432 433 ... 434 --- 435 436 # GCN-LABEL: name: v_interp 437 438 # GCN-LABEL: bb.0: 439 # GCN: S_MOV_B32 440 # GFX9-NEXT: S_NOP 441 # GCN-NEXT: V_INTERP_P1_F32 442 443 # GCN-LABEL: bb.1: 444 # GCN: S_MOV_B32 445 # GFX9-NEXT: S_NOP 446 # GCN-NEXT: V_INTERP_P2_F32 447 448 # GCN-LABEL: bb.2: 449 # GCN: S_MOV_B32 450 # GFX9-NEXT: S_NOP 451 # GCN-NEXT: V_INTERP_P1_F32_16bank 452 453 # GCN-LABEL: bb.3: 454 # GCN: S_MOV_B32 455 # GFX9-NEXT: S_NOP 456 # GCN-NEXT: V_INTERP_MOV_F32 457 458 name: v_interp 459 460 body: | 461 bb.0: 462 $m0 = S_MOV_B32 0 463 $vgpr0 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec 464 S_BRANCH %bb.1 465 466 bb.1: 467 $m0 = S_MOV_B32 0 468 $vgpr0 = V_INTERP_P2_F32 $vgpr0, $vgpr1, 0, 0, implicit $m0, implicit $exec 469 S_BRANCH %bb.2 470 471 bb.2: 472 $m0 = S_MOV_B32 0 473 $vgpr0 = V_INTERP_P1_F32_16bank $vgpr0, 0, 0, implicit $m0, implicit $exec 474 S_BRANCH %bb.3 475 476 bb.3: 477 $m0 = S_MOV_B32 0 478 $vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit $m0, implicit $exec 479 S_ENDPGM 480 ... 481 482 ... 483 --- 484 485 # GCN-LABEL: name: dpp 486 487 # VI-LABEL: bb.0: 488 # VI: V_MOV_B32_e32 489 # VI-NEXT: S_NOP 0 490 # VI-NEXT: S_NOP 0 491 # VI-NEXT: V_MOV_B32_dpp 492 493 # VI-LABEL: bb.1: 494 # VI: V_CMPX_EQ_I32_e32 495 # VI-NEXT: S_NOP 0 496 # VI-NEXT: S_NOP 0 497 # VI-NEXT: S_NOP 0 498 # VI-NEXT: S_NOP 0 499 # VI-NEXT: S_NOP 0 500 # VI-NEXT: V_MOV_B32_dpp 501 502 name: dpp 503 504 body: | 505 bb.0: 506 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 507 $vgpr1 = V_MOV_B32_dpp $vgpr1, $vgpr0, 0, 15, 15, 0, implicit $exec 508 S_BRANCH %bb.1 509 510 bb.1: 511 implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec 512 $vgpr3 = V_MOV_B32_dpp $vgpr3, $vgpr0, 0, 15, 15, 0, implicit $exec 513 S_ENDPGM 514 ... 515 --- 516 name: mov_fed_hazard_crash_on_dbg_value 517 alignment: 0 518 exposesReturnsTwice: false 519 legalized: false 520 regBankSelected: false 521 selected: false 522 tracksRegLiveness: true 523 liveins: 524 - { reg: '$sgpr4_sgpr5' } 525 - { reg: '$sgpr6_sgpr7' } 526 - { reg: '$sgpr9' } 527 - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 528 frameInfo: 529 isFrameAddressTaken: false 530 isReturnAddressTaken: false 531 hasStackMap: false 532 hasPatchPoint: false 533 stackSize: 16 534 offsetAdjustment: 0 535 maxAlignment: 8 536 adjustsStack: false 537 hasCalls: false 538 maxCallFrameSize: 0 539 hasOpaqueSPAdjustment: false 540 hasVAStart: false 541 hasMustTailInVarArgFunc: false 542 stack: 543 - { id: 0, name: A.addr, offset: 0, size: 8, alignment: 8, local-offset: 0 } 544 - { id: 1, offset: 8, size: 4, alignment: 4 } 545 body: | 546 bb.0.entry: 547 liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9, $sgpr0_sgpr1_sgpr2_sgpr3 548 549 $flat_scr_lo = S_ADD_U32 $sgpr6, $sgpr9, implicit-def $scc 550 $flat_scr_hi = S_ADDC_U32 $sgpr7, 0, implicit-def $scc, implicit $scc 551 DBG_VALUE $noreg, 2, !5, !11, debug-location !12 552 $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) 553 dead $sgpr6_sgpr7 = KILL $sgpr4_sgpr5 554 $sgpr8 = S_MOV_B32 $sgpr5 555 $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec 556 BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 4, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr + 4) 557 $sgpr8 = S_MOV_B32 $sgpr4, implicit killed $sgpr4_sgpr5 558 $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec 559 BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr) 560 S_ENDPGM 561 562 ... 563
