1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 3 ; Make sure that m0 is not reinitialized in the loop. 4 5 ; GCN-LABEL: {{^}}copy_local_to_global_loop_m0_init: 6 ; GCN: s_cbranch_scc1 BB0_3 7 8 ; Initialize in preheader 9 ; GCN: s_mov_b32 m0, -1 10 11 ; GCN: BB0_2: 12 ; GCN-NOT: m0 13 ; GCN: ds_read_b32 14 ; GCN-NOT: m0 15 ; GCN: buffer_store_dword 16 17 ; GCN: s_cbranch_scc0 BB0_2 18 19 ; GCN: BB0_3: 20 ; GCN-NEXT: s_endpgm 21 define amdgpu_kernel void @copy_local_to_global_loop_m0_init(i32 addrspace(1)* noalias nocapture %out, i32 addrspace(3)* noalias nocapture readonly %in, i32 %n) #0 { 22 bb: 23 %tmp = icmp sgt i32 %n, 0 24 br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge 25 26 .lr.ph.preheader: ; preds = %bb 27 br label %.lr.ph 28 29 ._crit_edge.loopexit: ; preds = %.lr.ph 30 br label %._crit_edge 31 32 ._crit_edge: ; preds = %._crit_edge.loopexit, %bb 33 ret void 34 35 .lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader 36 %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ] 37 %i.01 = phi i32 [ %tmp4, %.lr.ph ], [ 0, %.lr.ph.preheader ] 38 %tmp1 = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %i.01 39 %tmp2 = load i32, i32 addrspace(3)* %tmp1, align 4 40 %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %indvars.iv 41 store i32 %tmp2, i32 addrspace(1)* %tmp3, align 4 42 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 43 %tmp4 = add nuw nsw i32 %i.01, 1 44 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 45 %exitcond = icmp eq i32 %lftr.wideiv, %n 46 br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph 47 } 48 49 attributes #0 = { nounwind } 50
