1 # RUN: llc -march=amdgcn -run-pass liveintervals -verify-machineinstrs -o /dev/null -debug-only=regalloc %s 2>&1 | FileCheck %s 2 # REQUIRES: asserts 3 # We currently maintain a main liveness range which operates like a superset of 4 # all subregister liveranges. We may need to create additional SSA values at 5 # merge point in this main liverange even though none of the subregister 6 # liveranges needed it. 7 # 8 # Should see three distinct value numbers: 9 # CHECK: %0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}} 10 --- | 11 define amdgpu_kernel void @test0() { ret void } 12 ... 13 --- 14 name: test0 15 registers: 16 - { id: 0, class: sreg_64 } 17 body: | 18 bb.0: 19 S_NOP 0, implicit-def undef %0.sub0 20 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc 21 S_BRANCH %bb.2 22 23 bb.1: 24 S_NOP 0, implicit-def %0.sub1 25 S_NOP 0, implicit %0.sub1 26 S_BRANCH %bb.2 27 28 bb.2: 29 S_NOP 0, implicit %0.sub0 30 ... 31
