1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4 ;CHECK-LABEL: {{^}}test1: 5 ;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:32 glc slc 6 define amdgpu_vs void @test1(i32 %a1, i32 %vaddr) { 7 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 8 call void @llvm.SI.tbuffer.store.v4i32(<4 x i32> undef, <4 x i32> %vdata, 9 i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 1, 10 i32 1, i32 0) 11 ret void 12 } 13 14 ;CHECK-LABEL: {{^}}test1_idx: 15 ;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 idxen offset:32 glc slc 16 define amdgpu_vs void @test1_idx(i32 %a1, i32 %vaddr) { 17 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 18 call void @llvm.SI.tbuffer.store.v4i32(<4 x i32> undef, <4 x i32> %vdata, 19 i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 0, i32 1, i32 1, 20 i32 1, i32 0) 21 ret void 22 } 23 24 ;CHECK-LABEL: {{^}}test1_scalar_offset: 25 ;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, {{s[0-9]+}} idxen offset:32 glc slc 26 define amdgpu_vs void @test1_scalar_offset(i32 %a1, i32 %vaddr, i32 inreg %soffset) { 27 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 28 call void @llvm.SI.tbuffer.store.v4i32(<4 x i32> undef, <4 x i32> %vdata, 29 i32 4, i32 %vaddr, i32 %soffset, i32 32, i32 14, i32 4, i32 0, i32 1, i32 1, 30 i32 1, i32 0) 31 ret void 32 } 33 34 ;CHECK-LABEL: {{^}}test1_no_glc_slc: 35 ;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offen offset:32 36 define amdgpu_vs void @test1_no_glc_slc(i32 %a1, i32 %vaddr) { 37 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 38 call void @llvm.SI.tbuffer.store.v4i32(<4 x i32> undef, <4 x i32> %vdata, 39 i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 0, 40 i32 0, i32 0) 41 ret void 42 } 43 44 ;CHECK-LABEL: {{^}}test2: 45 ;CHECK: tbuffer_store_format_xyz {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:13, nfmt:4, 0 offen offset:24 glc slc 46 define amdgpu_vs void @test2(i32 %a1, i32 %vaddr) { 47 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 48 call void @llvm.SI.tbuffer.store.v4i32(<4 x i32> undef, <4 x i32> %vdata, 49 i32 3, i32 %vaddr, i32 0, i32 24, i32 13, i32 4, i32 1, i32 0, i32 1, 50 i32 1, i32 0) 51 ret void 52 } 53 54 ;CHECK-LABEL: {{^}}test3: 55 ;CHECK: tbuffer_store_format_xy {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:11, nfmt:4, 0 offen offset:16 glc slc 56 define amdgpu_vs void @test3(i32 %a1, i32 %vaddr) { 57 %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0 58 call void @llvm.SI.tbuffer.store.v2i32(<4 x i32> undef, <2 x i32> %vdata, 59 i32 2, i32 %vaddr, i32 0, i32 16, i32 11, i32 4, i32 1, i32 0, i32 1, 60 i32 1, i32 0) 61 ret void 62 } 63 64 ;CHECK-LABEL: {{^}}test4: 65 ;CHECK: tbuffer_store_format_x {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, dfmt:4, nfmt:4, 0 offen offset:8 glc slc 66 define amdgpu_vs void @test4(i32 %vdata, i32 %vaddr) { 67 call void @llvm.SI.tbuffer.store.i32(<4 x i32> undef, i32 %vdata, 68 i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1, 69 i32 1, i32 0) 70 ret void 71 } 72 73 declare void @llvm.SI.tbuffer.store.i32(<4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) 74 declare void @llvm.SI.tbuffer.store.v2i32(<4 x i32>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) 75 declare void @llvm.SI.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) 76
