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      1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
      2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
      3 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
      4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
      5 
      6 ; GCN-LABEL: {{^}}s_cvt_pk_i16_i32:
      7 ; GCN-DAG: s_load_dwordx2 s{{\[}}[[SX:[0-9]+]]:[[SY:[0-9]+]]{{\]}}, s[0:1], 0x{{b|2c}}
      8 ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
      9 ; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
     10 ; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, s[[SX]], [[VY]]
     11 define amdgpu_kernel void @s_cvt_pk_i16_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
     12   %result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %y)
     13   %r = bitcast <2 x i16> %result to i32
     14   store i32 %r, i32 addrspace(1)* %out
     15   ret void
     16 }
     17 
     18 ; GCN-LABEL: {{^}}s_cvt_pk_i16_samereg_i32:
     19 ; GCN: s_load_dword [[X:s[0-9]+]]
     20 ; GCN: v_cvt_pk_i16_i32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]
     21 define amdgpu_kernel void @s_cvt_pk_i16_samereg_i32(i32 addrspace(1)* %out, i32 %x) #0 {
     22   %result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %x)
     23   %r = bitcast <2 x i16> %result to i32
     24   store i32 %r, i32 addrspace(1)* %out
     25   ret void
     26 }
     27 
     28 ; GCN-LABEL: {{^}}v_cvt_pk_i16_i32:
     29 ; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
     30 ; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
     31 ; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, [[A]], [[B]]
     32 ; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, [[A]], [[B]]
     33 define amdgpu_kernel void @v_cvt_pk_i16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
     34   %tid = call i32 @llvm.amdgcn.workitem.id.x()
     35   %tid.ext = sext i32 %tid to i64
     36   %a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
     37   %b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr, i64 %tid.ext
     38   %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
     39   %a = load volatile i32, i32 addrspace(1)* %a.gep
     40   %b = load volatile i32, i32 addrspace(1)* %b.gep
     41   %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 %b)
     42   %r = bitcast <2 x i16> %cvt to i32
     43   store i32 %r, i32 addrspace(1)* %out.gep
     44   ret void
     45 }
     46 
     47 ; GCN-LABEL: {{^}}v_cvt_pk_i16_i32_reg_imm:
     48 ; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
     49 ; GCN: v_cvt_pk_i16_i32{{(_e64)*}} v{{[0-9]+}}, [[A]], 1
     50 define amdgpu_kernel void @v_cvt_pk_i16_i32_reg_imm(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
     51   %tid = call i32 @llvm.amdgcn.workitem.id.x()
     52   %tid.ext = sext i32 %tid to i64
     53   %a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
     54   %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
     55   %a = load volatile i32, i32 addrspace(1)* %a.gep
     56   %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 1)
     57   %r = bitcast <2 x i16> %cvt to i32
     58   store i32 %r, i32 addrspace(1)* %out.gep
     59   ret void
     60 }
     61 
     62 ; GCN-LABEL: {{^}}v_cvt_pk_i16_i32_imm_reg:
     63 ; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
     64 ; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, 1, [[A]]
     65 ; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, 1, [[A]]
     66 define amdgpu_kernel void @v_cvt_pk_i16_i32_imm_reg(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
     67   %tid = call i32 @llvm.amdgcn.workitem.id.x()
     68   %tid.ext = sext i32 %tid to i64
     69   %a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
     70   %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
     71   %a = load volatile i32, i32 addrspace(1)* %a.gep
     72   %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 1, i32 %a)
     73   %r = bitcast <2 x i16> %cvt to i32
     74   store i32 %r, i32 addrspace(1)* %out.gep
     75   ret void
     76 }
     77 
     78 declare <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32, i32) #1
     79 declare i32 @llvm.amdgcn.workitem.id.x() #1
     80 
     81 
     82 attributes #0 = { nounwind }
     83 attributes #1 = { nounwind readnone }
     84