1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s 3 4 declare float @llvm.amdgcn.div.fixup.f32(float, float, float) nounwind readnone 5 declare double @llvm.amdgcn.div.fixup.f64(double, double, double) nounwind readnone 6 7 ; GCN-LABEL: {{^}}test_div_fixup_f32: 8 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13 9 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 10 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x25 11 12 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 13 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70 14 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x94 15 16 ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] 17 ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] 18 ; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] 19 ; GCN: buffer_store_dword [[RESULT]], 20 ; GCN: s_endpgm 21 define amdgpu_kernel void @test_div_fixup_f32(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c) nounwind { 22 %result = call float @llvm.amdgcn.div.fixup.f32(float %a, float %b, float %c) nounwind readnone 23 store float %result, float addrspace(1)* %out, align 4 24 ret void 25 } 26 27 ; GCN-LABEL: {{^}}test_div_fixup_f64: 28 ; GCN: v_div_fixup_f64 29 define amdgpu_kernel void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { 30 %result = call double @llvm.amdgcn.div.fixup.f64(double %a, double %b, double %c) nounwind readnone 31 store double %result, double addrspace(1)* %out, align 8 32 ret void 33 } 34
