1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4 ; GCN-LABEL: {{^}}atomic_swap_1d: 5 ; GCN: image_atomic_swap v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 6 define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 7 main_body: 8 %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 9 %out = bitcast i32 %v to float 10 ret float %out 11 } 12 13 ; GCN-LABEL: {{^}}atomic_add_1d: 14 ; GCN: image_atomic_add v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 15 define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 16 main_body: 17 %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 18 %out = bitcast i32 %v to float 19 ret float %out 20 } 21 22 ; GCN-LABEL: {{^}}atomic_sub_1d: 23 ; GCN: image_atomic_sub v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 24 define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 25 main_body: 26 %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 27 %out = bitcast i32 %v to float 28 ret float %out 29 } 30 31 ; GCN-LABEL: {{^}}atomic_smin_1d: 32 ; GCN: image_atomic_smin v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 33 define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 34 main_body: 35 %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 36 %out = bitcast i32 %v to float 37 ret float %out 38 } 39 40 ; GCN-LABEL: {{^}}atomic_umin_1d: 41 ; GCN: image_atomic_umin v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 42 define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 43 main_body: 44 %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 45 %out = bitcast i32 %v to float 46 ret float %out 47 } 48 49 ; GCN-LABEL: {{^}}atomic_smax_1d: 50 ; GCN: image_atomic_smax v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 51 define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 52 main_body: 53 %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 54 %out = bitcast i32 %v to float 55 ret float %out 56 } 57 58 ; GCN-LABEL: {{^}}atomic_umax_1d: 59 ; GCN: image_atomic_umax v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 60 define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 61 main_body: 62 %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 63 %out = bitcast i32 %v to float 64 ret float %out 65 } 66 67 ; GCN-LABEL: {{^}}atomic_and_1d: 68 ; GCN: image_atomic_and v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 69 define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 70 main_body: 71 %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 72 %out = bitcast i32 %v to float 73 ret float %out 74 } 75 76 ; GCN-LABEL: {{^}}atomic_or_1d: 77 ; GCN: image_atomic_or v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 78 define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 79 main_body: 80 %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 81 %out = bitcast i32 %v to float 82 ret float %out 83 } 84 85 ; GCN-LABEL: {{^}}atomic_xor_1d: 86 ; GCN: image_atomic_xor v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 87 define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 88 main_body: 89 %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 90 %out = bitcast i32 %v to float 91 ret float %out 92 } 93 94 ; GCN-LABEL: {{^}}atomic_inc_1d: 95 ; GCN: image_atomic_inc v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 96 define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 97 main_body: 98 %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 99 %out = bitcast i32 %v to float 100 ret float %out 101 } 102 103 ; GCN-LABEL: {{^}}atomic_dec_1d: 104 ; GCN: image_atomic_dec v0, v1, s[0:7] dmask:0x1 unorm glc{{$}} 105 define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 106 main_body: 107 %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 108 %out = bitcast i32 %v to float 109 ret float %out 110 } 111 112 ; GCN-LABEL: {{^}}atomic_cmpswap_1d: 113 ; GCN: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 unorm glc{{$}} 114 define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i32 %s) { 115 main_body: 116 %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 117 %out = bitcast i32 %v to float 118 ret float %out 119 } 120 121 ; GCN-LABEL: {{^}}atomic_add_2d: 122 ; GCN: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc{{$}} 123 define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t) { 124 main_body: 125 %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 %data, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) 126 %out = bitcast i32 %v to float 127 ret float %out 128 } 129 130 ; GCN-LABEL: {{^}}atomic_add_3d: 131 ; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc{{$}} 132 define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %r) { 133 main_body: 134 %v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i32(i32 %data, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0) 135 %out = bitcast i32 %v to float 136 ret float %out 137 } 138 139 ; GCN-LABEL: {{^}}atomic_add_cube: 140 ; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc da{{$}} 141 define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %face) { 142 main_body: 143 %v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i32(i32 %data, i32 %s, i32 %t, i32 %face, <8 x i32> %rsrc, i32 0, i32 0) 144 %out = bitcast i32 %v to float 145 ret float %out 146 } 147 148 ; GCN-LABEL: {{^}}atomic_add_1darray: 149 ; GCN: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 unorm glc da{{$}} 150 define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %slice) { 151 main_body: 152 %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i32(i32 %data, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 153 %out = bitcast i32 %v to float 154 ret float %out 155 } 156 157 ; GCN-LABEL: {{^}}atomic_add_2darray: 158 ; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc da{{$}} 159 define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice) { 160 main_body: 161 %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 162 %out = bitcast i32 %v to float 163 ret float %out 164 } 165 166 ; GCN-LABEL: {{^}}atomic_add_2dmsaa: 167 ; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc{{$}} 168 define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %fragid) { 169 main_body: 170 %v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) 171 %out = bitcast i32 %v to float 172 ret float %out 173 } 174 175 ; GCN-LABEL: {{^}}atomic_add_2darraymsaa: 176 ; GCN: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 unorm glc da{{$}} 177 define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid) { 178 main_body: 179 %v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) 180 %out = bitcast i32 %v to float 181 ret float %out 182 } 183 184 ; GCN-LABEL: {{^}}atomic_add_1d_slc: 185 ; GCN: image_atomic_add v0, v1, s[0:7] dmask:0x1 unorm glc slc{{$}} 186 define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { 187 main_body: 188 %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 2) 189 %out = bitcast i32 %v to float 190 ret float %out 191 } 192 193 declare i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 194 declare i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 195 declare i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 196 declare i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 197 declare i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 198 declare i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 199 declare i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 200 declare i32 @llvm.amdgcn.image.atomic.and.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 201 declare i32 @llvm.amdgcn.image.atomic.or.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 202 declare i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 203 declare i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 204 declare i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) #0 205 declare i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0 206 207 declare i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0 208 declare i32 @llvm.amdgcn.image.atomic.add.3d.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0 209 declare i32 @llvm.amdgcn.image.atomic.add.cube.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0 210 declare i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0 211 declare i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0 212 declare i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0 213 declare i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #0 214 215 attributes #0 = { nounwind } 216 attributes #1 = { nounwind readonly } 217 attributes #2 = { nounwind readnone } 218
