1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 3 4 declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone 5 6 ; SI-LABEL: {{^}}test_trig_preop_f64: 7 ; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]] 8 ; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], 9 ; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]] 10 ; SI: buffer_store_dwordx2 [[RESULT]], 11 ; SI: s_endpgm 12 define amdgpu_kernel void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { 13 %a = load double, double addrspace(1)* %aptr, align 8 14 %b = load i32, i32 addrspace(1)* %bptr, align 4 15 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone 16 store double %result, double addrspace(1)* %out, align 8 17 ret void 18 } 19 20 ; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment: 21 ; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], 22 ; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7 23 ; SI: buffer_store_dwordx2 [[RESULT]], 24 ; SI: s_endpgm 25 define amdgpu_kernel void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind { 26 %a = load double, double addrspace(1)* %aptr, align 8 27 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone 28 store double %result, double addrspace(1)* %out, align 8 29 ret void 30 } 31
