1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8_9 %s 3 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GFX8_9 %s 4 5 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 6 declare float @llvm.fabs.f32(float) nounwind readnone 7 8 ; GCN-LABEL: {{^}}madak_f32: 9 ; GFX6: buffer_load_dword [[VA:v[0-9]+]] 10 ; GFX6: buffer_load_dword [[VB:v[0-9]+]] 11 ; GFX8_9: {{flat|global}}_load_dword [[VB:v[0-9]+]] 12 ; GFX8_9: {{flat|global}}_load_dword [[VA:v[0-9]+]] 13 ; GCN: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 14 define amdgpu_kernel void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { 15 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 16 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid 17 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid 18 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 19 20 %a = load float, float addrspace(1)* %in.a.gep, align 4 21 %b = load float, float addrspace(1)* %in.b.gep, align 4 22 23 %mul = fmul float %a, %b 24 %madak = fadd float %mul, 10.0 25 store float %madak, float addrspace(1)* %out.gep, align 4 26 ret void 27 } 28 29 ; Make sure this is only folded with one use. This is a code size 30 ; optimization and if we fold the immediate multiple times, we'll undo 31 ; it. 32 33 ; GCN-LABEL: {{^}}madak_2_use_f32: 34 ; GFX8_9: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 35 ; GFX6-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 36 ; GFX6-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 37 ; GFX6-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 38 ; GFX8_9: {{flat|global}}_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}} 39 ; GFX8_9: {{flat|global}}_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}} 40 ; GFX8_9: {{flat|global}}_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}} 41 ; GFX6-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 42 ; GCN-DAG: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 43 ; GCN-DAG: v_mac_f32_e32 [[VK]], [[VA]], [[VC]] 44 ; GCN: s_endpgm 45 define amdgpu_kernel void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { 46 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 47 48 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 49 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 50 %in.gep.2 = getelementptr float, float addrspace(1)* %in.gep.0, i32 2 51 52 %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid 53 %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 54 55 %a = load volatile float, float addrspace(1)* %in.gep.0, align 4 56 %b = load volatile float, float addrspace(1)* %in.gep.1, align 4 57 %c = load volatile float, float addrspace(1)* %in.gep.2, align 4 58 59 %mul0 = fmul float %a, %b 60 %mul1 = fmul float %a, %c 61 %madak0 = fadd float %mul0, 10.0 62 %madak1 = fadd float %mul1, 10.0 63 64 store volatile float %madak0, float addrspace(1)* %out.gep.0, align 4 65 store volatile float %madak1, float addrspace(1)* %out.gep.1, align 4 66 ret void 67 } 68 69 ; GCN-LABEL: {{^}}madak_m_inline_imm_f32: 70 ; GCN: {{buffer|flat|global}}_load_dword [[VA:v[0-9]+]] 71 ; GCN: v_madak_f32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000 72 define amdgpu_kernel void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a) nounwind { 73 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 74 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid 75 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 76 77 %a = load float, float addrspace(1)* %in.a.gep, align 4 78 79 %mul = fmul float 4.0, %a 80 %madak = fadd float %mul, 10.0 81 store float %madak, float addrspace(1)* %out.gep, align 4 82 ret void 83 } 84 85 ; Make sure nothing weird happens with a value that is also allowed as 86 ; an inline immediate. 87 88 ; GCN-LABEL: {{^}}madak_inline_imm_f32: 89 ; GFX6: buffer_load_dword [[VA:v[0-9]+]] 90 ; GFX6: buffer_load_dword [[VB:v[0-9]+]] 91 ; GFX8_9: {{flat|global}}_load_dword [[VB:v[0-9]+]] 92 ; GFX8_9: {{flat|global}}_load_dword [[VA:v[0-9]+]] 93 ; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0 94 define amdgpu_kernel void @madak_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { 95 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 96 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid 97 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid 98 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 99 100 %a = load float, float addrspace(1)* %in.a.gep, align 4 101 %b = load float, float addrspace(1)* %in.b.gep, align 4 102 103 %mul = fmul float %a, %b 104 %madak = fadd float %mul, 4.0 105 store float %madak, float addrspace(1)* %out.gep, align 4 106 ret void 107 } 108 109 ; We can't use an SGPR when forming madak 110 ; GCN-LABEL: {{^}}s_v_madak_f32: 111 ; GCN-DAG: s_load_dword [[SB:s[0-9]+]] 112 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 113 ; GCN-DAG: {{buffer|flat|global}}_load_dword [[VA:v[0-9]+]] 114 ; GCN-NOT: v_madak_f32 115 ; GCN: v_mac_f32_e32 [[VK]], [[SB]], [[VA]] 116 define amdgpu_kernel void @s_v_madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float %b) nounwind { 117 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 118 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid 119 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 120 121 %a = load float, float addrspace(1)* %in.a.gep, align 4 122 123 %mul = fmul float %a, %b 124 %madak = fadd float %mul, 10.0 125 store float %madak, float addrspace(1)* %out.gep, align 4 126 ret void 127 } 128 129 ; GCN-LABEL: @v_s_madak_f32 130 ; GCN-DAG: s_load_dword [[SB:s[0-9]+]] 131 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 132 ; GCN-DAG: {{buffer|flat|global}}_load_dword [[VA:v[0-9]+]] 133 ; GCN-NOT: v_madak_f32 134 ; GCN: v_mac_f32_e32 [[VK]], [[SB]], [[VA]] 135 define amdgpu_kernel void @v_s_madak_f32(float addrspace(1)* noalias %out, float %a, float addrspace(1)* noalias %in.b) nounwind { 136 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 137 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid 138 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 139 140 %b = load float, float addrspace(1)* %in.b.gep, align 4 141 142 %mul = fmul float %a, %b 143 %madak = fadd float %mul, 10.0 144 store float %madak, float addrspace(1)* %out.gep, align 4 145 ret void 146 } 147 148 ; GCN-LABEL: {{^}}s_s_madak_f32: 149 ; GCN-NOT: v_madak_f32 150 ; GCN: v_mac_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 151 define amdgpu_kernel void @s_s_madak_f32(float addrspace(1)* %out, float %a, float %b) nounwind { 152 %mul = fmul float %a, %b 153 %madak = fadd float %mul, 10.0 154 store float %madak, float addrspace(1)* %out, align 4 155 ret void 156 } 157 158 ; GCN-LABEL: {{^}}no_madak_src0_modifier_f32: 159 ; GFX6: buffer_load_dword [[VA:v[0-9]+]] 160 ; GFX6: buffer_load_dword [[VB:v[0-9]+]] 161 ; GFX8_9: {{flat|global}}_load_dword [[VB:v[0-9]+]] 162 ; GFX8_9: {{flat|global}}_load_dword [[VA:v[0-9]+]] 163 ; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}} 164 ; GCN: s_endpgm 165 define amdgpu_kernel void @no_madak_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { 166 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 167 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid 168 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid 169 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 170 171 %a = load float, float addrspace(1)* %in.a.gep, align 4 172 %b = load float, float addrspace(1)* %in.b.gep, align 4 173 174 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone 175 176 %mul = fmul float %a.fabs, %b 177 %madak = fadd float %mul, 10.0 178 store float %madak, float addrspace(1)* %out.gep, align 4 179 ret void 180 } 181 182 ; GCN-LABEL: {{^}}no_madak_src1_modifier_f32: 183 ; GFX6: buffer_load_dword [[VA:v[0-9]+]] 184 ; GFX6: buffer_load_dword [[VB:v[0-9]+]] 185 ; GFX8_9: {{flat|global}}_load_dword [[VB:v[0-9]+]] 186 ; GFX8_9: {{flat|global}}_load_dword [[VA:v[0-9]+]] 187 ; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|, {{[sv][0-9]+}} 188 ; GCN: s_endpgm 189 define amdgpu_kernel void @no_madak_src1_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { 190 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 191 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid 192 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid 193 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 194 195 %a = load float, float addrspace(1)* %in.a.gep, align 4 196 %b = load float, float addrspace(1)* %in.b.gep, align 4 197 198 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone 199 200 %mul = fmul float %a, %b.fabs 201 %madak = fadd float %mul, 10.0 202 store float %madak, float addrspace(1)* %out.gep, align 4 203 ret void 204 } 205 206 ; SIFoldOperands should not fold the SGPR copy into the instruction 207 ; because the implicit immediate already uses the constant bus. 208 ; GCN-LABEL: {{^}}madak_constant_bus_violation: 209 ; GCN: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x12|0x48}} 210 ; GCN: v_mov_b32_e32 [[SGPR0_VCOPY:v[0-9]+]], [[SGPR0]] 211 ; GCN: {{buffer|flat|global}}_load_dword [[VGPR:v[0-9]+]] 212 ; GCN: v_madak_f32 [[MADAK:v[0-9]+]], 0.5, [[SGPR0_VCOPY]], 0x42280000 213 ; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[MADAK]], [[VGPR]] 214 ; GFX6: buffer_store_dword [[MUL]] 215 ; GFX8_9: {{flat|global}}_store_dword v[{{[0-9:]+}}], [[MUL]] 216 define amdgpu_kernel void @madak_constant_bus_violation(i32 %arg1, [8 x i32], float %sgpr0, float %sgpr1) #0 { 217 bb: 218 %tmp = icmp eq i32 %arg1, 0 219 br i1 %tmp, label %bb3, label %bb4 220 221 bb3: 222 store volatile float 0.0, float addrspace(1)* undef 223 br label %bb4 224 225 bb4: 226 %vgpr = load volatile float, float addrspace(1)* undef 227 %tmp0 = fmul float %sgpr0, 0.5 228 %tmp1 = fadd float %tmp0, 42.0 229 %tmp2 = fmul float %tmp1, %vgpr 230 store volatile float %tmp2, float addrspace(1)* undef, align 4 231 ret void 232 } 233 234 attributes #0 = { nounwind} 235
