1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s 3 4 ; Make sure there isn't an extra space between the instruction name and first operands. 5 6 ; GCN-LABEL: {{^}}add_f32: 7 ; SI: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c 8 ; SI: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13 9 ; SI: v_mov_b32_e32 [[VREGA:v[0-9]+]], [[SREGA]] 10 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGB]], [[VREGA]] 11 12 ; VI: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c 13 ; VI: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70 14 ; VI: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]] 15 ; VI: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]] 16 17 ; GCN: buffer_store_dword [[RESULT]], 18 define amdgpu_kernel void @add_f32(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b) { 19 %result = fadd float %a, %b 20 store float %result, float addrspace(1)* %out 21 ret void 22 } 23
