1 # RUN: llc -march=amdgcn -run-pass si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s 2 3 # Check that constant is in SGPR registers 4 5 # GCN-LABEL: {{^}}name: const_to_sgpr{{$}} 6 # GCN: %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 7 # GCN-NEXT: %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576 8 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1 9 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit $exec 10 11 12 # GCN-LABEL: {{^}}name: const_to_sgpr_multiple_use{{$}} 13 # GCN: %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 14 # GCN-NEXT: %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576 15 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1 16 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit $exec 17 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit $exec 18 19 # GCN-LABEL: {{^}}name: const_to_sgpr_subreg{{$}} 20 # GCN: %[[OP0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, %subreg.sub0, killed %{{[0-9]+}}, %subreg.sub1 21 # GCN-NEXT: V_CMP_LT_U32_e64 killed %[[OP0]].sub0, 12, implicit $exec 22 23 --- | 24 define amdgpu_kernel void @const_to_sgpr(i32 addrspace(1)* nocapture %arg, i64 %id) { 25 bb: 26 br i1 undef, label %bb1, label %bb2 27 28 bb1: ; preds = %bb 29 br label %bb2 30 31 bb2: ; preds = %bb1, %bb 32 ret void 33 } 34 35 define amdgpu_kernel void @const_to_sgpr_multiple_use(i32 addrspace(1)* nocapture %arg, i64 %id1, i64 %id2) { 36 bb: 37 br i1 undef, label %bb1, label %bb2 38 39 bb1: ; preds = %bb 40 br label %bb2 41 42 bb2: ; preds = %bb1, %bb 43 ret void 44 } 45 46 define amdgpu_kernel void @const_to_sgpr_subreg(i32 addrspace(1)* nocapture %arg, i64 %id) { 47 bb: 48 br i1 undef, label %bb1, label %bb2 49 50 bb1: ; preds = %bb 51 br label %bb2 52 53 bb2: ; preds = %bb1, %bb 54 ret void 55 } 56 57 ... 58 --- 59 name: const_to_sgpr 60 alignment: 0 61 exposesReturnsTwice: false 62 legalized: false 63 regBankSelected: false 64 selected: false 65 tracksRegLiveness: true 66 registers: 67 - { id: 0, class: sreg_64 } 68 - { id: 1, class: sreg_64 } 69 - { id: 2, class: vgpr_32 } 70 - { id: 3, class: sgpr_64 } 71 - { id: 4, class: sreg_32_xm0 } 72 - { id: 5, class: sgpr_32 } 73 - { id: 6, class: sreg_64 } 74 - { id: 7, class: sreg_64_xexec } 75 - { id: 8, class: sreg_64_xexec } 76 - { id: 9, class: sreg_32 } 77 - { id: 10, class: sreg_64 } 78 - { id: 11, class: sreg_32_xm0 } 79 - { id: 12, class: sreg_32_xm0 } 80 - { id: 13, class: sreg_32_xm0 } 81 - { id: 14, class: sreg_32_xm0 } 82 - { id: 15, class: sreg_32_xm0 } 83 - { id: 16, class: sreg_32_xm0 } 84 - { id: 17, class: sreg_64 } 85 - { id: 18, class: sreg_32_xm0 } 86 - { id: 19, class: sreg_32_xm0 } 87 - { id: 20, class: sreg_64 } 88 - { id: 21, class: sreg_64 } 89 - { id: 22, class: vreg_64 } 90 - { id: 23, class: sreg_32_xm0 } 91 - { id: 24, class: sreg_64 } 92 - { id: 25, class: sreg_32_xm0 } 93 - { id: 26, class: sreg_32_xm0 } 94 - { id: 27, class: sgpr_64 } 95 - { id: 28, class: sgpr_128 } 96 - { id: 29, class: vgpr_32 } 97 - { id: 30, class: vreg_64 } 98 liveins: 99 - { reg: '$vgpr0', virtual-reg: '%2' } 100 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 101 body: | 102 bb.0.bb: 103 successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000) 104 liveins: $vgpr0, $sgpr0_sgpr1 105 106 %3 = COPY $sgpr0_sgpr1 107 %2 = COPY $vgpr0 108 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0 109 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0 110 %6 = COPY %7 111 %9 = S_MOV_B32 0 112 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1 113 %0 = COPY %10 114 %11 = COPY %10.sub0 115 %12 = COPY %10.sub1 116 %13 = COPY %8.sub0 117 %14 = COPY %8.sub1 118 %15 = S_ADD_U32 killed %11, killed %13, implicit-def $scc 119 %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead $scc, implicit $scc 120 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1 121 %18 = S_MOV_B32 0 122 %19 = S_MOV_B32 1048576 123 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1 124 %22 = COPY killed %20 125 %21 = V_CMP_LT_U64_e64 killed %17, %22, implicit $exec 126 %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 127 S_BRANCH %bb.1.bb1 128 129 bb.1.bb1: 130 successors: %bb.2.bb2(0x80000000) 131 132 %23 = S_MOV_B32 2 133 %24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc 134 %25 = S_MOV_B32 61440 135 %26 = S_MOV_B32 0 136 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1 137 %28 = REG_SEQUENCE %6, 17, killed %27, 18 138 %29 = V_MOV_B32_e32 0, implicit $exec 139 %30 = COPY %24 140 BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit $exec 141 142 bb.2.bb2: 143 SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 144 S_ENDPGM 145 146 ... 147 --- 148 name: const_to_sgpr_multiple_use 149 alignment: 0 150 exposesReturnsTwice: false 151 legalized: false 152 regBankSelected: false 153 selected: false 154 tracksRegLiveness: true 155 registers: 156 - { id: 0, class: sreg_64 } 157 - { id: 1, class: sreg_64 } 158 - { id: 2, class: vgpr_32 } 159 - { id: 3, class: sgpr_64 } 160 - { id: 4, class: sreg_32_xm0 } 161 - { id: 5, class: sgpr_32 } 162 - { id: 6, class: sreg_64 } 163 - { id: 7, class: sreg_64_xexec } 164 - { id: 8, class: sreg_64_xexec } 165 - { id: 9, class: sreg_64_xexec } 166 - { id: 10, class: sreg_32 } 167 - { id: 11, class: sreg_64 } 168 - { id: 12, class: sreg_32_xm0 } 169 - { id: 13, class: sreg_32_xm0 } 170 - { id: 14, class: sreg_32_xm0 } 171 - { id: 15, class: sreg_32_xm0 } 172 - { id: 16, class: sreg_32_xm0 } 173 - { id: 17, class: sreg_32_xm0 } 174 - { id: 18, class: sreg_64 } 175 - { id: 19, class: sreg_32_xm0 } 176 - { id: 20, class: sreg_32_xm0 } 177 - { id: 21, class: sreg_32_xm0 } 178 - { id: 22, class: sreg_32_xm0 } 179 - { id: 23, class: sreg_64 } 180 - { id: 24, class: sreg_32_xm0 } 181 - { id: 25, class: sreg_32_xm0 } 182 - { id: 26, class: sreg_64 } 183 - { id: 27, class: sreg_64 } 184 - { id: 28, class: vreg_64 } 185 - { id: 29, class: sreg_64 } 186 - { id: 30, class: vreg_64 } 187 - { id: 31, class: sreg_64 } 188 - { id: 32, class: sreg_32_xm0 } 189 - { id: 33, class: sreg_64 } 190 - { id: 34, class: sreg_32_xm0 } 191 - { id: 35, class: sreg_32_xm0 } 192 - { id: 36, class: sgpr_64 } 193 - { id: 37, class: sgpr_128 } 194 - { id: 38, class: vgpr_32 } 195 - { id: 39, class: vreg_64 } 196 liveins: 197 - { reg: '$vgpr0', virtual-reg: '%2' } 198 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 199 body: | 200 bb.0.bb: 201 successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000) 202 liveins: $vgpr0, $sgpr0_sgpr1 203 204 %3 = COPY $sgpr0_sgpr1 205 %2 = COPY $vgpr0 206 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0 207 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0 208 %9 = S_LOAD_DWORDX2_IMM %3, 13, 0 209 %6 = COPY %7 210 %10 = S_MOV_B32 0 211 %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1 212 %0 = COPY %11 213 %12 = COPY %11.sub0 214 %13 = COPY %11.sub1 215 %14 = COPY %8.sub0 216 %15 = COPY %8.sub1 217 %16 = S_ADD_U32 %12, killed %14, implicit-def $scc 218 %17 = S_ADDC_U32 %13, killed %15, implicit-def dead $scc, implicit $scc 219 %18 = REG_SEQUENCE killed %16, %subreg.sub0, killed %17, %subreg.sub1 220 %19 = COPY %9.sub0 221 %20 = COPY %9.sub1 222 %21 = S_ADD_U32 %12, killed %19, implicit-def $scc 223 %22 = S_ADDC_U32 %13, killed %20, implicit-def dead $scc, implicit $scc 224 %23 = REG_SEQUENCE killed %21, %subreg.sub0, killed %22, %subreg.sub1 225 %24 = S_MOV_B32 0 226 %25 = S_MOV_B32 1048576 227 %26 = REG_SEQUENCE killed %25, %subreg.sub0, killed %24, %subreg.sub1 228 %28 = COPY %26 229 %27 = V_CMP_LT_U64_e64 killed %18, %28, implicit $exec 230 %29 = V_CMP_LT_U64_e64 killed %23, %28, implicit $exec 231 %31 = S_AND_B64 killed %27, killed %29, implicit-def dead $scc 232 %1 = SI_IF killed %31, %bb.2.bb2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 233 S_BRANCH %bb.1.bb1 234 235 bb.1.bb1: 236 successors: %bb.2.bb2(0x80000000) 237 238 %32 = S_MOV_B32 2 239 %33 = S_LSHL_B64 %0, killed %32, implicit-def dead $scc 240 %34 = S_MOV_B32 61440 241 %35 = S_MOV_B32 0 242 %36 = REG_SEQUENCE killed %35, %subreg.sub0, killed %34, %subreg.sub1 243 %37 = REG_SEQUENCE %6, 17, killed %36, 18 244 %38 = V_MOV_B32_e32 0, implicit $exec 245 %39 = COPY %33 246 BUFFER_STORE_DWORD_ADDR64 killed %38, killed %39, killed %37, 0, 0, 0, 0, 0, implicit $exec 247 248 bb.2.bb2: 249 SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 250 S_ENDPGM 251 252 ... 253 --- 254 name: const_to_sgpr_subreg 255 alignment: 0 256 exposesReturnsTwice: false 257 legalized: false 258 regBankSelected: false 259 selected: false 260 tracksRegLiveness: true 261 registers: 262 - { id: 0, class: sreg_64 } 263 - { id: 1, class: sreg_64 } 264 - { id: 2, class: vgpr_32 } 265 - { id: 3, class: sgpr_64 } 266 - { id: 4, class: sreg_32_xm0 } 267 - { id: 5, class: sgpr_32 } 268 - { id: 6, class: sreg_64 } 269 - { id: 7, class: sreg_64_xexec } 270 - { id: 8, class: sreg_64_xexec } 271 - { id: 9, class: sreg_32 } 272 - { id: 10, class: sreg_64 } 273 - { id: 11, class: sreg_32_xm0 } 274 - { id: 12, class: sreg_32_xm0 } 275 - { id: 13, class: sreg_32_xm0 } 276 - { id: 14, class: sreg_32_xm0 } 277 - { id: 15, class: sreg_32_xm0 } 278 - { id: 16, class: sreg_32_xm0 } 279 - { id: 17, class: sreg_64 } 280 - { id: 18, class: sreg_32_xm0 } 281 - { id: 19, class: sreg_32_xm0 } 282 - { id: 20, class: sreg_64 } 283 - { id: 21, class: sreg_64 } 284 - { id: 22, class: vgpr_32 } 285 - { id: 23, class: sreg_32_xm0 } 286 - { id: 24, class: sreg_64 } 287 - { id: 25, class: sreg_32_xm0 } 288 - { id: 26, class: sreg_32_xm0 } 289 - { id: 27, class: sgpr_64 } 290 - { id: 28, class: sgpr_128 } 291 - { id: 29, class: vgpr_32 } 292 - { id: 30, class: vreg_64 } 293 liveins: 294 - { reg: '$vgpr0', virtual-reg: '%2' } 295 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 296 body: | 297 bb.0.bb: 298 successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000) 299 liveins: $vgpr0, $sgpr0_sgpr1 300 301 %3 = COPY $sgpr0_sgpr1 302 %2 = COPY $vgpr0 303 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0 304 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0 305 %6 = COPY %7 306 %9 = S_MOV_B32 0 307 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1 308 %0 = COPY %10 309 %11 = COPY %10.sub0 310 %12 = COPY %10.sub1 311 %13 = COPY %8.sub0 312 %14 = COPY %8.sub1 313 %15 = S_ADD_U32 killed %11, killed %13, implicit-def $scc 314 %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead $scc, implicit $scc 315 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1 316 %18 = S_MOV_B32 12 317 %19 = S_MOV_B32 1048576 318 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1 319 %22 = COPY killed %20.sub1 320 %21 = V_CMP_LT_U32_e64 killed %17.sub0, %22, implicit $exec 321 %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 322 S_BRANCH %bb.1.bb1 323 324 bb.1.bb1: 325 successors: %bb.2.bb2(0x80000000) 326 327 %23 = S_MOV_B32 2 328 %24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc 329 %25 = S_MOV_B32 61440 330 %26 = S_MOV_B32 0 331 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1 332 %28 = REG_SEQUENCE %6, 17, killed %27, 18 333 %29 = V_MOV_B32_e32 0, implicit $exec 334 %30 = COPY %24 335 BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, 0, implicit $exec 336 337 bb.2.bb2: 338 SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 339 S_ENDPGM 340 341 ... 342
