1 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 2 ; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 3 4 ; TODO: Add _RTN versions and merge with the GCN test 5 6 ; FUNC-LABEL: {{^}}atomic_add_i32_offset: 7 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]] 8 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 9 define amdgpu_kernel void @atomic_add_i32_offset(i32 addrspace(1)* %out, i32 %in) { 10 entry: 11 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 12 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 13 ret void 14 } 15 16 ; FUNC-LABEL: {{^}}atomic_add_i32_soffset: 17 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]] 18 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 19 define amdgpu_kernel void @atomic_add_i32_soffset(i32 addrspace(1)* %out, i32 %in) { 20 entry: 21 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 9000 22 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 23 ret void 24 } 25 26 ; FUNC-LABEL: {{^}}atomic_add_i32_huge_offset: 27 ; FIXME: looks like the offset is wrong 28 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]] 29 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 30 define amdgpu_kernel void @atomic_add_i32_huge_offset(i32 addrspace(1)* %out, i32 %in) { 31 entry: 32 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 47224239175595 33 34 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 35 ret void 36 } 37 38 ; FUNC-LABEL: {{^}}atomic_add_i32_addr64_offset: 39 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]] 40 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 41 define amdgpu_kernel void @atomic_add_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 42 entry: 43 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 44 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 45 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 46 ret void 47 } 48 49 ; FUNC-LABEL: {{^}}atomic_add_i32: 50 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]] 51 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 52 define amdgpu_kernel void @atomic_add_i32(i32 addrspace(1)* %out, i32 %in) { 53 entry: 54 %val = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst 55 ret void 56 } 57 58 ; FUNC-LABEL: {{^}}atomic_add_i32_addr64: 59 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]] 60 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 61 define amdgpu_kernel void @atomic_add_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 62 entry: 63 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 64 %val = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst 65 ret void 66 } 67 68 ; FUNC-LABEL: {{^}}atomic_and_i32_offset: 69 ; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]] 70 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 71 define amdgpu_kernel void @atomic_and_i32_offset(i32 addrspace(1)* %out, i32 %in) { 72 entry: 73 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 74 %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst 75 ret void 76 } 77 78 ; FUNC-LABEL: {{^}}atomic_and_i32_addr64_offset: 79 ; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]] 80 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 81 define amdgpu_kernel void @atomic_and_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 82 entry: 83 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 84 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 85 %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst 86 ret void 87 } 88 89 ; FUNC-LABEL: {{^}}atomic_and_i32: 90 ; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]] 91 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 92 define amdgpu_kernel void @atomic_and_i32(i32 addrspace(1)* %out, i32 %in) { 93 entry: 94 %val = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst 95 ret void 96 } 97 98 ; FUNC-LABEL: {{^}}atomic_and_i32_addr64: 99 ; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]] 100 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 101 define amdgpu_kernel void @atomic_and_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 102 entry: 103 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 104 %val = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst 105 ret void 106 } 107 108 ; FUNC-LABEL: {{^}}atomic_sub_i32_offset: 109 ; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]] 110 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 111 define amdgpu_kernel void @atomic_sub_i32_offset(i32 addrspace(1)* %out, i32 %in) { 112 entry: 113 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 114 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst 115 ret void 116 } 117 118 ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64_offset: 119 ; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]] 120 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 121 define amdgpu_kernel void @atomic_sub_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 122 entry: 123 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 124 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 125 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst 126 ret void 127 } 128 129 ; FUNC-LABEL: {{^}}atomic_sub_i32: 130 ; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]] 131 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 132 define amdgpu_kernel void @atomic_sub_i32(i32 addrspace(1)* %out, i32 %in) { 133 entry: 134 %val = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst 135 ret void 136 } 137 138 ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64: 139 ; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]] 140 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 141 define amdgpu_kernel void @atomic_sub_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 142 entry: 143 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 144 %val = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst 145 ret void 146 } 147 148 ; FUNC-LABEL: {{^}}atomic_max_i32_offset: 149 ; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]] 150 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 151 define amdgpu_kernel void @atomic_max_i32_offset(i32 addrspace(1)* %out, i32 %in) { 152 entry: 153 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 154 %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst 155 ret void 156 } 157 158 ; FUNC-LABEL: {{^}}atomic_max_i32_addr64_offset: 159 ; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]] 160 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 161 define amdgpu_kernel void @atomic_max_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 162 entry: 163 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 164 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 165 %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst 166 ret void 167 } 168 169 ; FUNC-LABEL: {{^}}atomic_max_i32: 170 ; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]] 171 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 172 define amdgpu_kernel void @atomic_max_i32(i32 addrspace(1)* %out, i32 %in) { 173 entry: 174 %val = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst 175 ret void 176 } 177 178 ; FUNC-LABEL: {{^}}atomic_max_i32_addr64: 179 ; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]] 180 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 181 define amdgpu_kernel void @atomic_max_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 182 entry: 183 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 184 %val = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst 185 ret void 186 } 187 188 ; FUNC-LABEL: {{^}}atomic_umax_i32_offset: 189 ; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]] 190 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 191 define amdgpu_kernel void @atomic_umax_i32_offset(i32 addrspace(1)* %out, i32 %in) { 192 entry: 193 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 194 %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst 195 ret void 196 } 197 198 ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64_offset: 199 ; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]] 200 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 201 define amdgpu_kernel void @atomic_umax_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 202 entry: 203 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 204 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 205 %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst 206 ret void 207 } 208 209 ; FUNC-LABEL: {{^}}atomic_umax_i32: 210 ; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]] 211 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 212 define amdgpu_kernel void @atomic_umax_i32(i32 addrspace(1)* %out, i32 %in) { 213 entry: 214 %val = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst 215 ret void 216 } 217 218 ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64: 219 ; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]] 220 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 221 define amdgpu_kernel void @atomic_umax_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 222 entry: 223 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 224 %val = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst 225 ret void 226 } 227 228 ; FUNC-LABEL: {{^}}atomic_min_i32_offset: 229 ; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]] 230 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 231 define amdgpu_kernel void @atomic_min_i32_offset(i32 addrspace(1)* %out, i32 %in) { 232 entry: 233 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 234 %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst 235 ret void 236 } 237 238 ; FUNC-LABEL: {{^}}atomic_min_i32_addr64_offset: 239 ; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]] 240 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 241 define amdgpu_kernel void @atomic_min_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 242 entry: 243 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 244 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 245 %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst 246 ret void 247 } 248 249 ; FUNC-LABEL: {{^}}atomic_min_i32: 250 ; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]] 251 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 252 define amdgpu_kernel void @atomic_min_i32(i32 addrspace(1)* %out, i32 %in) { 253 entry: 254 %val = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst 255 ret void 256 } 257 258 ; FUNC-LABEL: {{^}}atomic_min_i32_addr64: 259 ; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]] 260 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 261 define amdgpu_kernel void @atomic_min_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 262 entry: 263 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 264 %val = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst 265 ret void 266 } 267 268 ; FUNC-LABEL: {{^}}atomic_umin_i32_offset: 269 ; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]] 270 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 271 define amdgpu_kernel void @atomic_umin_i32_offset(i32 addrspace(1)* %out, i32 %in) { 272 entry: 273 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 274 %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst 275 ret void 276 } 277 278 ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64_offset: 279 ; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]] 280 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 281 define amdgpu_kernel void @atomic_umin_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 282 entry: 283 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 284 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 285 %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst 286 ret void 287 } 288 289 ; FUNC-LABEL: {{^}}atomic_umin_i32: 290 ; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]] 291 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 292 define amdgpu_kernel void @atomic_umin_i32(i32 addrspace(1)* %out, i32 %in) { 293 entry: 294 %val = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst 295 ret void 296 } 297 298 ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64: 299 ; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]] 300 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 301 define amdgpu_kernel void @atomic_umin_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 302 entry: 303 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 304 %val = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst 305 ret void 306 } 307 308 ; FUNC-LABEL: {{^}}atomic_or_i32_offset: 309 ; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]] 310 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 311 define amdgpu_kernel void @atomic_or_i32_offset(i32 addrspace(1)* %out, i32 %in) { 312 entry: 313 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 314 %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst 315 ret void 316 } 317 318 ; FUNC-LABEL: {{^}}atomic_or_i32_addr64_offset: 319 ; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]] 320 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 321 define amdgpu_kernel void @atomic_or_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 322 entry: 323 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 324 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 325 %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst 326 ret void 327 } 328 329 ; FUNC-LABEL: {{^}}atomic_or_i32: 330 ; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]] 331 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 332 define amdgpu_kernel void @atomic_or_i32(i32 addrspace(1)* %out, i32 %in) { 333 entry: 334 %val = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst 335 ret void 336 } 337 338 ; FUNC-LABEL: {{^}}atomic_or_i32_addr64: 339 ; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]] 340 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 341 define amdgpu_kernel void @atomic_or_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 342 entry: 343 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 344 %val = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst 345 ret void 346 } 347 348 ; FUNC-LABEL: {{^}}atomic_xchg_i32_offset: 349 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 350 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 351 define amdgpu_kernel void @atomic_xchg_i32_offset(i32 addrspace(1)* %out, i32 %in) { 352 entry: 353 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 354 %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst 355 ret void 356 } 357 358 ; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64_offset: 359 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 360 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 361 define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 362 entry: 363 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 364 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 365 %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst 366 ret void 367 } 368 369 ; FUNC-LABEL: {{^}}atomic_xchg_i32: 370 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 371 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 372 define amdgpu_kernel void @atomic_xchg_i32(i32 addrspace(1)* %out, i32 %in) { 373 entry: 374 %val = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst 375 ret void 376 } 377 378 ; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64: 379 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 380 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 381 define amdgpu_kernel void @atomic_xchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 382 entry: 383 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 384 %val = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst 385 ret void 386 } 387 388 ; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_offset: 389 ; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]] 390 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 391 define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32 addrspace(1)* %out, i32 %in, i32 %old) { 392 entry: 393 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 394 %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst 395 ret void 396 } 397 398 ; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset: 399 ; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]] 400 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 401 define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) { 402 entry: 403 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 404 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 405 %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst 406 ret void 407 } 408 409 ; FUNC-LABEL: {{^}}atomic_cmpxchg_i32: 410 ; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]] 411 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 412 define amdgpu_kernel void @atomic_cmpxchg_i32(i32 addrspace(1)* %out, i32 %in, i32 %old) { 413 entry: 414 %val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst 415 ret void 416 } 417 418 ; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_addr64: 419 ; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]] 420 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 421 define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) { 422 entry: 423 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 424 %val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst 425 ret void 426 } 427 428 ; FUNC-LABEL: {{^}}atomic_xor_i32_offset: 429 ; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]] 430 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 431 define amdgpu_kernel void @atomic_xor_i32_offset(i32 addrspace(1)* %out, i32 %in) { 432 entry: 433 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 434 %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst 435 ret void 436 } 437 438 ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64_offset: 439 ; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]] 440 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 441 define amdgpu_kernel void @atomic_xor_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 442 entry: 443 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 444 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 445 %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst 446 ret void 447 } 448 449 ; FUNC-LABEL: {{^}}atomic_xor_i32: 450 ; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]] 451 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 452 define amdgpu_kernel void @atomic_xor_i32(i32 addrspace(1)* %out, i32 %in) { 453 entry: 454 %val = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst 455 ret void 456 } 457 458 ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64: 459 ; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]] 460 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z 461 define amdgpu_kernel void @atomic_xor_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 462 entry: 463 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 464 %val = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst 465 ret void 466 } 467 468 ; FUNC-LABEL: {{^}}atomic_store_i32_offset: 469 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 470 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y 471 define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, i32 addrspace(1)* %out) { 472 entry: 473 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 474 store atomic i32 %in, i32 addrspace(1)* %gep seq_cst, align 4 475 ret void 476 } 477 478 ; FUNC-LABEL: {{^}}atomic_store_i32: 479 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 480 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y 481 define amdgpu_kernel void @atomic_store_i32(i32 %in, i32 addrspace(1)* %out) { 482 entry: 483 store atomic i32 %in, i32 addrspace(1)* %out seq_cst, align 4 484 ret void 485 } 486 487 ; FUNC-LABEL: {{^}}atomic_store_i32_addr64_offset: 488 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 489 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y 490 define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, i32 addrspace(1)* %out, i64 %index) { 491 entry: 492 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 493 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 494 store atomic i32 %in, i32 addrspace(1)* %gep seq_cst, align 4 495 ret void 496 } 497 498 ; FUNC-LABEL: {{^}}atomic_store_i32_addr64: 499 ; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]] 500 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y 501 define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, i32 addrspace(1)* %out, i64 %index) { 502 entry: 503 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 504 store atomic i32 %in, i32 addrspace(1)* %ptr seq_cst, align 4 505 ret void 506 } 507 508 ; FUNC-LABEL: {{^}}atomic_inc_add 509 ; EG: MEM_RAT ATOMIC_INC_UINT 510 define amdgpu_kernel void @atomic_inc_add(i32 addrspace(1)* %out) { 511 entry: 512 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 513 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 1 seq_cst 514 ret void 515 } 516 517 ; FUNC-LABEL: {{^}}atomic_dec_add 518 ; EG: MEM_RAT ATOMIC_DEC_UINT 519 define amdgpu_kernel void @atomic_dec_add(i32 addrspace(1)* %out) { 520 entry: 521 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 522 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 -1 seq_cst 523 ret void 524 } 525 526 ; FUNC-LABEL: {{^}}atomic_inc_sub 527 ; EG: MEM_RAT ATOMIC_INC_UINT 528 define amdgpu_kernel void @atomic_inc_sub(i32 addrspace(1)* %out) { 529 entry: 530 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 531 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 -1 seq_cst 532 ret void 533 } 534 535 ; FUNC-LABEL: {{^}}atomic_dec_sub 536 ; EG: MEM_RAT ATOMIC_DEC_UINT 537 define amdgpu_kernel void @atomic_dec_sub(i32 addrspace(1)* %out) { 538 entry: 539 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 540 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 1 seq_cst 541 ret void 542 } 543
