1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 3 ; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4: 4 ; GCN: s_load_dwordx2 5 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} 6 define amdgpu_kernel void @store_v2i32_as_v4i16_align_4(<4 x i16> addrspace(3)* align 4 %out, <2 x i32> %x) #0 { 7 %x.bc = bitcast <2 x i32> %x to <4 x i16> 8 store <4 x i16> %x.bc, <4 x i16> addrspace(3)* %out, align 4 9 ret void 10 } 11 12 ; GCN-LABEL: {{^}}store_v4i32_as_v8i16_align_4: 13 ; GCN: s_load_dwordx4 14 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 15 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} 16 define amdgpu_kernel void @store_v4i32_as_v8i16_align_4(<8 x i16> addrspace(3)* align 4 %out, <4 x i32> %x) #0 { 17 %x.bc = bitcast <4 x i32> %x to <8 x i16> 18 store <8 x i16> %x.bc, <8 x i16> addrspace(3)* %out, align 4 19 ret void 20 } 21 22 ; GCN-LABEL: {{^}}store_v2i32_as_i64_align_4: 23 ; GCN: s_load_dwordx2 24 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} 25 define amdgpu_kernel void @store_v2i32_as_i64_align_4(<4 x i16> addrspace(3)* align 4 %out, <2 x i32> %x) #0 { 26 %x.bc = bitcast <2 x i32> %x to <4 x i16> 27 store <4 x i16> %x.bc, <4 x i16> addrspace(3)* %out, align 4 28 ret void 29 } 30 31 ; GCN-LABEL: {{^}}store_v4i32_as_v2i64_align_4: 32 ; GCN: s_load_dwordx4 33 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 34 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} 35 define amdgpu_kernel void @store_v4i32_as_v2i64_align_4(<2 x i64> addrspace(3)* align 4 %out, <4 x i32> %x) #0 { 36 %x.bc = bitcast <4 x i32> %x to <2 x i64> 37 store <2 x i64> %x.bc, <2 x i64> addrspace(3)* %out, align 4 38 ret void 39 } 40 41 ; GCN-LABEL: {{^}}store_v4i16_as_v2i32_align_4: 42 ; GCN: s_load_dword s 43 ; GCN-NEXT: s_load_dwordx2 s 44 ; GCN-NOT: {{buffer|flat|global}} 45 46 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} 47 define amdgpu_kernel void @store_v4i16_as_v2i32_align_4(<2 x i32> addrspace(3)* align 4 %out, <4 x i16> %x) #0 { 48 %x.bc = bitcast <4 x i16> %x to <2 x i32> 49 store <2 x i32> %x.bc, <2 x i32> addrspace(3)* %out, align 4 50 ret void 51 } 52 53 attributes #0 = { nounwind } 54
