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      1 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck %s
      2 --- |
      3   define amdgpu_kernel void @test0() { ret void }
      4   define amdgpu_kernel void @test1() { ret void }
      5   define amdgpu_kernel void @test2() { ret void }
      6 ...
      7 ---
      8 # In the test below we have two independent def+use pairs of subregister1 which
      9 # can be moved to a new virtual register. The third def of sub1 however is used
     10 # in combination with sub0 and needs to stay with the original vreg.
     11 # CHECK-LABEL: name: test0
     12 # CHECK: S_NOP 0, implicit-def undef %0.sub0
     13 # CHECK: S_NOP 0, implicit-def undef %2.sub1
     14 # CHECK: S_NOP 0, implicit %2.sub1
     15 # CHECK: S_NOP 0, implicit-def undef %1.sub1
     16 # CHECK: S_NOP 0, implicit %1.sub1
     17 # CHECK: S_NOP 0, implicit-def %0.sub1
     18 # CHECK: S_NOP 0, implicit %0
     19 name: test0
     20 registers:
     21   - { id: 0, class: sreg_128 }
     22 body: |
     23   bb.0:
     24     S_NOP 0, implicit-def undef %0.sub0
     25     S_NOP 0, implicit-def %0.sub1
     26     S_NOP 0, implicit %0.sub1
     27     S_NOP 0, implicit-def %0.sub1
     28     S_NOP 0, implicit %0.sub1
     29     S_NOP 0, implicit-def %0.sub1
     30     S_NOP 0, implicit %0
     31 ...
     32 ---
     33 # Test for a bug where we would incorrectly query liveness at the instruction
     34 # index in rewriteOperands(). This should pass the verifier afterwards.
     35 # CHECK-LABEL: test1
     36 # CHECK: bb.0
     37 # CHECK: S_NOP 0, implicit-def undef %2.sub2
     38 # CHECK: bb.1
     39 # CHECK: S_NOP 0, implicit-def %2.sub1
     40 # CHECK-NEXT: S_NOP 0, implicit-def %2.sub3
     41 # CHECK-NEXT: S_NOP 0, implicit %2
     42 # CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub0
     43 # CHECK-NEXT: S_NOP 0, implicit %2.sub1
     44 # CHECK-NEXT: S_NOP 0, implicit %0.sub0
     45 # CHECK: bb.2
     46 # CHECK: S_NOP 0, implicit %2.sub
     47 name: test1
     48 registers:
     49   - { id: 0, class: sreg_128 }
     50   - { id: 1, class: sreg_128 }
     51 body: |
     52   bb.0:
     53     S_NOP 0, implicit-def undef %0.sub2
     54     S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
     55     S_BRANCH %bb.2
     56 
     57   bb.1:
     58     S_NOP 0, implicit-def %0.sub1
     59     S_NOP 0, implicit-def %0.sub3
     60     %1 = COPY %0
     61     S_NOP 0, implicit %1
     62 
     63     S_NOP 0, implicit-def %1.sub0
     64     S_NOP 0, implicit %1.sub1
     65     S_NOP 0, implicit %1.sub0
     66 
     67   bb.2:
     68     S_NOP 0, implicit %0.sub2
     69 
     70 ...
     71 # In this test, there are two pairs of tied operands
     72 # within the inline asm statement:
     73 # (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
     74 # Check that renaming (2) does not inadvertently rename (1).
     75 # CHECK-LABEL: name: test2
     76 # CHECK: INLINEASM &"", 32, 327690, def undef %0.sub0, 327690, def dead %1.sub1, 2147483657, undef %0.sub0(tied-def 3), 2147549193, %1.sub1(tied-def 5)
     77 name: test2
     78 body: |
     79   bb.0:
     80     undef %0.sub0:vreg_64 = IMPLICIT_DEF
     81 
     82   bb.1:
     83     undef %0.sub1:vreg_64 = V_ALIGNBIT_B32 %0.sub0:vreg_64, %0.sub0:vreg_64, 16, implicit $exec
     84     INLINEASM &"", 32, 327690, def undef %0.sub0:vreg_64, 327690, def %0.sub1:vreg_64, 2147483657, undef %0.sub0:vreg_64(tied-def 3), 2147549193, %0.sub1:vreg_64(tied-def 5)
     85     S_BRANCH %bb.1
     86 
     87 ...
     88