1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2 3 ; -------------------------------------------------------------------------------- 4 ; Don't fold if fneg can fold into the source 5 ; -------------------------------------------------------------------------------- 6 7 ; GCN-LABEL: {{^}}select_fneg_posk_src_rcp_legacy_f32: 8 ; GCN: buffer_load_dword [[X:v[0-9]+]] 9 10 ; GCN: v_rcp_legacy_f32_e32 [[RCP:v[0-9]+]], [[X]] 11 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc 12 ; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]] 13 ; GCN-NEXT: buffer_store_dword [[NEG_SELECT]] 14 define amdgpu_kernel void @select_fneg_posk_src_rcp_legacy_f32(i32 %c) #2 { 15 %x = load volatile float, float addrspace(1)* undef 16 %y = load volatile float, float addrspace(1)* undef 17 %cmp = icmp eq i32 %c, 0 18 %rcp = call float @llvm.amdgcn.rcp.legacy(float %x) 19 %fneg = fsub float -0.0, %rcp 20 %select = select i1 %cmp, float %fneg, float 2.0 21 store volatile float %select, float addrspace(1)* undef 22 ret void 23 } 24 25 ; GCN-LABEL: {{^}}select_fneg_posk_src_mul_legacy_f32: 26 ; GCN: buffer_load_dword [[X:v[0-9]+]] 27 28 ; GCN: v_mul_legacy_f32_e32 [[MUL:v[0-9]+]], 4.0, [[X]] 29 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[MUL]], vcc 30 ; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]] 31 ; GCN-NEXT: buffer_store_dword [[NEG_SELECT]] 32 define amdgpu_kernel void @select_fneg_posk_src_mul_legacy_f32(i32 %c) #2 { 33 %x = load volatile float, float addrspace(1)* undef 34 %cmp = icmp eq i32 %c, 0 35 %mul = call float @llvm.amdgcn.fmul.legacy(float %x, float 4.0) 36 %fneg = fsub float -0.0, %mul 37 %select = select i1 %cmp, float %fneg, float 2.0 38 store volatile float %select, float addrspace(1)* undef 39 ret void 40 } 41 42 declare float @llvm.amdgcn.rcp.legacy(float) #1 43 declare float @llvm.amdgcn.fmul.legacy(float, float) #1 44 45 attributes #0 = { nounwind } 46 attributes #1 = { nounwind readnone } 47
