1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s 2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s 3 4 ; FIXME: This should go in existing select.ll test, except the current testcase there is broken on GCN 5 6 ; GCN-LABEL: {{^}}select_i1: 7 ; GCN: v_cndmask_b32 8 ; GCN-NOT: v_cndmask_b32 9 define amdgpu_kernel void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind { 10 %cmp = icmp ugt i32 %cond, 5 11 %sel = select i1 %cmp, i1 %a, i1 %b 12 store i1 %sel, i1 addrspace(1)* %out, align 4 13 ret void 14 } 15 16 ; GCN-LABEL: {{^}}s_minmax_i1: 17 ; GCN: s_load_dword [[LOAD:s[0-9]+]], 18 ; GCN-DAG: s_lshr_b32 [[A:s[0-9]+]], [[LOAD]], 8 19 ; GCN-DAG: s_lshr_b32 [[B:s[0-9]+]], [[LOAD]], 16 20 ; GCN-DAG: s_and_b32 [[COND:s[0-9]+]], 1, [[LOAD]] 21 ; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]] 22 ; GCN: v_mov_b32_e32 [[V_A:v[0-9]+]], [[A]] 23 ; GCN: v_cmp_eq_u32_e64 vcc, [[COND]], 1 24 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], [[V_B]], [[V_A]] 25 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, [[SEL]] 26 define amdgpu_kernel void @s_minmax_i1(i1 addrspace(1)* %out, [8 x i32], i1 zeroext %cond, i1 zeroext %a, i1 zeroext %b) nounwind { 27 %cmp = icmp slt i1 %cond, false 28 %sel = select i1 %cmp, i1 %a, i1 %b 29 store i1 %sel, i1 addrspace(1)* %out, align 4 30 ret void 31 } 32
