1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s 3 4 ; CHECK-LABEL: {{^}}phi1: 5 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 6 ; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]] 7 define amdgpu_ps void @phi1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 8 main_body: 9 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 10 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 11 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0) 12 %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16) 13 %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32) 14 %tmp24 = fptosi float %tmp22 to i32 15 %tmp25 = icmp ne i32 %tmp24, 0 16 br i1 %tmp25, label %ENDIF, label %ELSE 17 18 ELSE: ; preds = %main_body 19 %tmp26 = fsub float -0.000000e+00, %tmp21 20 br label %ENDIF 21 22 ENDIF: ; preds = %ELSE, %main_body 23 %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ] 24 %tmp27 = fadd float %temp.0, %tmp23 25 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0 26 ret void 27 } 28 29 ; Make sure this program doesn't crash 30 ; CHECK-LABEL: {{^}}phi2: 31 define amdgpu_ps void @phi2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 { 32 main_body: 33 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 34 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 35 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16) 36 %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32) 37 %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 36) 38 %tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 40) 39 %tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 48) 40 %tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 52) 41 %tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 56) 42 %tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 64) 43 %tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 68) 44 %tmp30 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 72) 45 %tmp31 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 76) 46 %tmp32 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 80) 47 %tmp33 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 84) 48 %tmp34 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 88) 49 %tmp35 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 92) 50 %tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %arg2, i32 0 51 %tmp37 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp36, !tbaa !0 52 %tmp38 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg1, i32 0 53 %tmp39 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp38, !tbaa !0 54 %i.i = extractelement <2 x i32> %arg5, i32 0 55 %j.i = extractelement <2 x i32> %arg5, i32 1 56 %i.f.i = bitcast i32 %i.i to float 57 %j.f.i = bitcast i32 %j.i to float 58 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1 59 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1 60 %i.i19 = extractelement <2 x i32> %arg5, i32 0 61 %j.i20 = extractelement <2 x i32> %arg5, i32 1 62 %i.f.i21 = bitcast i32 %i.i19 to float 63 %j.f.i22 = bitcast i32 %j.i20 to float 64 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #1 65 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #1 66 %i.i13 = extractelement <2 x i32> %arg5, i32 0 67 %j.i14 = extractelement <2 x i32> %arg5, i32 1 68 %i.f.i15 = bitcast i32 %i.i13 to float 69 %j.f.i16 = bitcast i32 %j.i14 to float 70 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #1 71 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #1 72 %i.i7 = extractelement <2 x i32> %arg5, i32 0 73 %j.i8 = extractelement <2 x i32> %arg5, i32 1 74 %i.f.i9 = bitcast i32 %i.i7 to float 75 %j.f.i10 = bitcast i32 %j.i8 to float 76 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #1 77 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #1 78 %i.i1 = extractelement <2 x i32> %arg5, i32 0 79 %j.i2 = extractelement <2 x i32> %arg5, i32 1 80 %i.f.i3 = bitcast i32 %i.i1 to float 81 %j.f.i4 = bitcast i32 %j.i2 to float 82 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #1 83 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #1 84 %tmp39.bc = bitcast <4 x i32> %tmp39 to <4 x i32> 85 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i24, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i1 0, i32 0, i32 0) 86 %tmp50 = extractelement <4 x float> %tmp1, i32 2 87 %tmp51 = call float @llvm.fabs.f32(float %tmp50) 88 %tmp52 = fmul float %p2.i18, %p2.i18 89 %tmp53 = fmul float %p2.i12, %p2.i12 90 %tmp54 = fadd float %tmp53, %tmp52 91 %tmp55 = fmul float %p2.i6, %p2.i6 92 %tmp56 = fadd float %tmp54, %tmp55 93 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56) 94 %tmp58 = fmul float %p2.i18, %tmp57 95 %tmp59 = fmul float %p2.i12, %tmp57 96 %tmp60 = fmul float %p2.i6, %tmp57 97 %tmp61 = fmul float %tmp58, %tmp22 98 %tmp62 = fmul float %tmp59, %tmp23 99 %tmp63 = fadd float %tmp62, %tmp61 100 %tmp64 = fmul float %tmp60, %tmp24 101 %tmp65 = fadd float %tmp63, %tmp64 102 %tmp66 = fsub float -0.000000e+00, %tmp25 103 %tmp67 = fmul float %tmp65, %tmp51 104 %tmp68 = fadd float %tmp67, %tmp66 105 %tmp69 = fmul float %tmp26, %tmp68 106 %tmp70 = fmul float %tmp27, %tmp68 107 %tmp71 = call float @llvm.fabs.f32(float %tmp69) 108 %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71 109 %tmp73 = sext i1 %tmp72 to i32 110 %tmp74 = bitcast i32 %tmp73 to float 111 %tmp75 = bitcast float %tmp74 to i32 112 %tmp76 = icmp ne i32 %tmp75, 0 113 br i1 %tmp76, label %IF, label %ENDIF 114 115 IF: ; preds = %main_body 116 %tmp77 = fsub float -0.000000e+00, %tmp69 117 %tmp78 = call float @llvm.exp2.f32(float %tmp77) 118 %tmp79 = fsub float -0.000000e+00, %tmp78 119 %tmp80 = fadd float 1.000000e+00, %tmp79 120 %tmp81 = fdiv float 1.000000e+00, %tmp69 121 %tmp82 = fmul float %tmp80, %tmp81 122 %tmp83 = fmul float %tmp31, %tmp82 123 br label %ENDIF 124 125 ENDIF: ; preds = %IF, %main_body 126 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ] 127 %tmp84 = call float @llvm.fabs.f32(float %tmp70) 128 %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84 129 %tmp86 = sext i1 %tmp85 to i32 130 %tmp87 = bitcast i32 %tmp86 to float 131 %tmp88 = bitcast float %tmp87 to i32 132 %tmp89 = icmp ne i32 %tmp88, 0 133 br i1 %tmp89, label %IF25, label %ENDIF24 134 135 IF25: ; preds = %ENDIF 136 %tmp90 = fsub float -0.000000e+00, %tmp70 137 %tmp91 = call float @llvm.exp2.f32(float %tmp90) 138 %tmp92 = fsub float -0.000000e+00, %tmp91 139 %tmp93 = fadd float 1.000000e+00, %tmp92 140 %tmp94 = fdiv float 1.000000e+00, %tmp70 141 %tmp95 = fmul float %tmp93, %tmp94 142 %tmp96 = fmul float %tmp35, %tmp95 143 br label %ENDIF24 144 145 ENDIF24: ; preds = %IF25, %ENDIF 146 %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ] 147 %tmp97 = fmul float %tmp28, %temp4.0 148 %tmp98 = fmul float %tmp29, %temp4.0 149 %tmp99 = fmul float %tmp30, %temp4.0 150 %tmp100 = fmul float %tmp32, %temp8.0 151 %tmp101 = fadd float %tmp100, %tmp97 152 %tmp102 = fmul float %tmp33, %temp8.0 153 %tmp103 = fadd float %tmp102, %tmp98 154 %tmp104 = fmul float %tmp34, %temp8.0 155 %tmp105 = fadd float %tmp104, %tmp99 156 %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21) 157 %tmp107 = fsub float -0.000000e+00, %tmp101 158 %tmp108 = fmul float %tmp107, %tmp106 159 %tmp109 = fsub float -0.000000e+00, %tmp103 160 %tmp110 = fmul float %tmp109, %tmp106 161 %tmp111 = fsub float -0.000000e+00, %tmp105 162 %tmp112 = fmul float %tmp111, %tmp106 163 %tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110) 164 %tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00) 165 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0 166 ret void 167 } 168 169 ; We just want ot make sure the program doesn't crash 170 ; CHECK-LABEL: {{^}}loop: 171 define amdgpu_ps void @loop(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 172 main_body: 173 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 174 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 175 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0) 176 %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 4) 177 %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 8) 178 %tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 12) 179 %tmp25 = fptosi float %tmp24 to i32 180 %tmp26 = bitcast i32 %tmp25 to float 181 %tmp27 = bitcast float %tmp26 to i32 182 br label %LOOP 183 184 LOOP: ; preds = %ENDIF, %main_body 185 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ] 186 %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ] 187 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ] 188 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ] 189 %tmp28 = bitcast float %temp8.0 to i32 190 %tmp29 = icmp sge i32 %tmp28, %tmp27 191 %tmp30 = sext i1 %tmp29 to i32 192 %tmp31 = bitcast i32 %tmp30 to float 193 %tmp32 = bitcast float %tmp31 to i32 194 %tmp33 = icmp ne i32 %tmp32, 0 195 br i1 %tmp33, label %IF, label %ENDIF 196 197 IF: ; preds = %LOOP 198 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00, i1 true, i1 true) #0 199 ret void 200 201 ENDIF: ; preds = %LOOP 202 %tmp34 = bitcast float %temp8.0 to i32 203 %tmp35 = add i32 %tmp34, 1 204 %tmp36 = bitcast i32 %tmp35 to float 205 br label %LOOP 206 } 207 208 ; This checks for a bug in the FixSGPRCopies pass where VReg96 209 ; registers were being identified as an SGPR regclass which was causing 210 ; an assertion failure. 211 212 ; CHECK-LABEL: {{^}}sample_v3: 213 ; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11 214 ; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13 215 ; CHECK: s_branch 216 217 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5 218 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7 219 220 ; CHECK: BB{{[0-9]+_[0-9]+}}: 221 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}} 222 ; CHECK: exp 223 ; CHECK: s_endpgm 224 define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 225 entry: 226 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0 227 %tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 228 %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 16) 229 %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0 230 %tmp24 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp23, !tbaa !0 231 %tmp25 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0 232 %tmp26 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp25, !tbaa !0 233 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00 234 %tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32> 235 br i1 %tmp27, label %if, label %else 236 237 if: ; preds = %entry 238 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36D6000000000000, float 0x36DA000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0) 239 %val.if.0 = extractelement <4 x float> %tmp1, i32 0 240 %val.if.1 = extractelement <4 x float> %tmp1, i32 1 241 %val.if.2 = extractelement <4 x float> %tmp1, i32 2 242 br label %endif 243 244 else: ; preds = %entry 245 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36C4000000000000, float 0x36CC000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0) 246 %val.else.0 = extractelement <4 x float> %tmp2, i32 0 247 %val.else.1 = extractelement <4 x float> %tmp2, i32 1 248 %val.else.2 = extractelement <4 x float> %tmp2, i32 2 249 br label %endif 250 251 endif: ; preds = %else, %if 252 %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ] 253 %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ] 254 %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ] 255 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %val.0, float %val.1, float %val.2, float 0.000000e+00, i1 true, i1 true) #0 256 ret void 257 } 258 259 ; CHECK-LABEL: {{^}}copy1: 260 ; CHECK: buffer_load_dword 261 ; CHECK: v_add 262 ; CHECK: s_endpgm 263 define amdgpu_kernel void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) { 264 entry: 265 %tmp = load float, float addrspace(1)* %in0 266 %tmp1 = fcmp oeq float %tmp, 0.000000e+00 267 br i1 %tmp1, label %if0, label %endif 268 269 if0: ; preds = %entry 270 %tmp2 = bitcast float %tmp to i32 271 %tmp3 = fcmp olt float %tmp, 0.000000e+00 272 br i1 %tmp3, label %if1, label %endif 273 274 if1: ; preds = %if0 275 %tmp4 = add i32 %tmp2, 1 276 br label %endif 277 278 endif: ; preds = %if1, %if0, %entry 279 %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ] 280 %tmp6 = bitcast i32 %tmp5 to float 281 store float %tmp6, float addrspace(1)* %out 282 ret void 283 } 284 285 ; This test is just checking that we don't crash / assertion fail. 286 ; CHECK-LABEL: {{^}}copy2: 287 ; CHECK: s_endpgm 288 define amdgpu_ps void @copy2([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 289 entry: 290 br label %LOOP68 291 292 LOOP68: ; preds = %ENDIF69, %entry 293 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] 294 %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] 295 %g = icmp eq i32 0, %t 296 %l = bitcast float %temp4.7 to i32 297 br i1 %g, label %IF70, label %ENDIF69 298 299 IF70: ; preds = %LOOP68 300 %q = icmp ne i32 %l, 13 301 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00 302 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0 303 ret void 304 305 ENDIF69: ; preds = %LOOP68 306 %u = add i32 %l, %t 307 %v = bitcast i32 %u to float 308 %x = add i32 %t, -1 309 br label %LOOP68 310 } 311 312 ; This test checks that image_sample resource descriptors aren't loaded into 313 ; vgprs. The verifier will fail if this happens. 314 ; CHECK-LABEL:{{^}}sample_rsrc 315 316 ; CHECK: s_cmp_eq_u32 317 ; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]] 318 319 ; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}} 320 321 ; [[END]]: 322 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}} 323 ; CHECK: s_endpgm 324 define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* byval %arg, [17 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <4 x i32>] addrspace(4)* byval %arg2, [32 x <8 x i32>] addrspace(4)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { 325 bb: 326 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i32 0, i32 0 327 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !3 328 %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp22, i32 16) 329 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(4)* %arg3, i32 0, i32 0 330 %tmp26 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp25, !tbaa !3 331 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(4)* %arg2, i32 0, i32 0 332 %tmp28 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp27, !tbaa !3 333 %i.i = extractelement <2 x i32> %arg7, i32 0 334 %j.i = extractelement <2 x i32> %arg7, i32 1 335 %i.f.i = bitcast i32 %i.i to float 336 %j.f.i = bitcast i32 %j.i to float 337 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0 338 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0 339 %i.i1 = extractelement <2 x i32> %arg7, i32 0 340 %j.i2 = extractelement <2 x i32> %arg7, i32 1 341 %i.f.i3 = bitcast i32 %i.i1 to float 342 %j.f.i4 = bitcast i32 %j.i2 to float 343 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #0 344 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #0 345 %tmp31 = bitcast float %tmp23 to i32 346 %tmp36 = icmp ne i32 %tmp31, 0 347 br i1 %tmp36, label %bb38, label %bb80 348 349 bb38: ; preds = %bb 350 %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32> 351 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp56, <4 x i32> %tmp28, i1 0, i32 0, i32 0) 352 br label %bb71 353 354 bb80: ; preds = %bb 355 %tmp81 = bitcast float %p2.i to i32 356 %tmp82 = bitcast float %p2.i6 to i32 357 %tmp82.2 = add i32 %tmp82, 1 358 %tmp83 = bitcast i32 %tmp81 to float 359 %tmp84 = bitcast i32 %tmp82.2 to float 360 %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32> 361 %tmp3 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp83, float %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i1 0, i32 0, i32 0) 362 br label %bb71 363 364 bb71: ; preds = %bb80, %bb38 365 %tmp72 = phi <4 x float> [ %tmp2, %bb38 ], [ %tmp3, %bb80 ] 366 %tmp88 = extractelement <4 x float> %tmp72, i32 0 367 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0 368 ret void 369 } 370 371 ; Check the resource descriptor is stored in an sgpr. 372 ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr: 373 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 374 define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(4)* byval %arg) #0 { 375 bb: 376 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 377 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(4)* %arg, i32 0, i32 %tid 378 %tmp8 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp7, align 32, !tbaa !0 379 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> %tmp8, <4 x i32> undef, i1 0, i32 0, i32 0) 380 %tmp10 = extractelement <4 x float> %tmp, i32 0 381 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10) 382 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 383 ret void 384 } 385 386 ; Check the sampler is stored in an sgpr. 387 ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr: 388 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 389 define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(4)* byval %arg) #0 { 390 bb: 391 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 392 %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i32 0, i32 %tid 393 %tmp8 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp7, align 16, !tbaa !0 394 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> undef, <4 x i32> %tmp8, i1 0, i32 0, i32 0) 395 %tmp10 = extractelement <4 x float> %tmp, i32 0 396 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) 397 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 398 ret void 399 } 400 401 declare float @llvm.fabs.f32(float) #1 402 declare float @llvm.amdgcn.rsq.f32(float) #1 403 declare float @llvm.exp2.f32(float) #1 404 declare float @llvm.pow.f32(float, float) #1 405 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 406 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1 407 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1 408 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 409 declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0 410 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 411 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 412 declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1 413 414 attributes #0 = { nounwind } 415 attributes #1 = { nounwind readnone } 416 attributes #2 = { nounwind readonly } 417 418 !0 = !{!1, !1, i64 0, i32 1} 419 !1 = !{!"const", !2} 420 !2 = !{!"tbaa root"} 421 !3 = !{!1, !1, i64 0} 422
