1 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -start-before=greedy -stop-after=stack-slot-coloring -o - %s | FileCheck -check-prefixes=SHARE,GCN %s 2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -start-before=greedy -stop-after=stack-slot-coloring -no-stack-slot-sharing -o - %s | FileCheck -check-prefixes=NOSHARE,GCN %s 3 4 # Make sure that stack slot coloring doesn't try to merge frame 5 # indexes used for SGPR spilling with those that aren't. 6 # Even when stack slot sharing was disabled, it was still moving the 7 # FI ID used for an SGPR spill to a normal frame index. 8 9 --- | 10 11 define void @sgpr_spill_wrong_stack_id(float addrspace(1)* nocapture readnone %arg, float addrspace(1)* noalias %arg1) { 12 bb: 13 %tmp = load i32, i32 addrspace(1)* null, align 4 14 call void @func(i32 undef) 15 call void @func(i32 %tmp) 16 unreachable 17 } 18 19 declare void @func(i32) 20 21 ... 22 --- 23 24 # GCN-LABEL: name: sgpr_spill_wrong_stack_id 25 # SHARE: stack: 26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, 27 # SHARE: stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4, 30 # SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true, 31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, 33 # SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true, 34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 35 36 # SHARE: SI_SPILL_S32_SAVE $sgpr5, %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 4 into %stack.2, addrspace 5) 37 # SHARE: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5) 38 # SHARE: SI_SPILL_S64_SAVE killed renamable $sgpr6_sgpr7, %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 8 into %stack.1, align 4, addrspace 5) 39 # SHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5) 40 # SHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0 41 # SHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.2, addrspace 5) 42 # SHARE: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5) 43 # SHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5) 44 # SHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0 45 # SHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.2, addrspace 5) 46 47 # NOSHARE: stack: 48 # NOSHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, 49 # NOSHARE: stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 50 # NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 51 # NOSHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4, 52 # NOSHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true, 53 # NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 54 # NOSHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, 55 # NOSHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true, 56 # NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 57 # NOSHARE: - { id: 3, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, 58 # NOSHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true, 59 # NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 60 61 # NOSHARE: SI_SPILL_S32_SAVE $sgpr5, %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 4 into %stack.2, addrspace 5) 62 # NOSHARE: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5) 63 # NOSHARE: SI_SPILL_S64_SAVE killed renamable $sgpr6_sgpr7, %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 8 into %stack.1, align 4, addrspace 5) 64 # NOSHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5) 65 # NOSHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0 66 # NOSHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.2, addrspace 5) 67 # NOSHARE: SI_SPILL_S32_SAVE $sgpr5, %stack.3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 4 into %stack.3, addrspace 5) 68 # NOSHARE: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5) 69 # NOSHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5) 70 # NOSHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0 71 # NOSHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.3, addrspace 5) 72 73 ... 74 75 name: sgpr_spill_wrong_stack_id 76 tracksRegLiveness: true 77 frameInfo: 78 adjustsStack: false 79 hasCalls: true 80 body: | 81 bb.0.bb: 82 %8:sreg_32_xm0 = COPY $sgpr5 83 %4:vreg_64 = IMPLICIT_DEF 84 %3:vgpr_32 = FLAT_LOAD_DWORD %4, 0, 0, 0, implicit $exec, implicit $flat_scr 85 %5:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc 86 ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 87 dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0 88 $sgpr5 = COPY %8 89 %12:sreg_32_xm0 = COPY $sgpr5 90 ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 91 ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 92 $vgpr0 = COPY %3 93 dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0 94 $sgpr5 = COPY %12 95 ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5 96 97 ... 98
