1 # RUN: llc -verify-machineinstrs -march=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s 2 # Check that add with carry out isn't incorrectly reduced to e32 when 3 # the carry out is a virtual register. 4 5 # TODO: We should run this test until the end of codegen to make sure 6 # that the post-RA run does manage to shrink it, but right now the 7 # resume crashes 8 9 ... 10 # GCN-LABEL: name: shrink_add_vop3{{$}} 11 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, implicit $exec 12 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec 13 name: shrink_add_vop3 14 alignment: 0 15 exposesReturnsTwice: false 16 legalized: false 17 regBankSelected: false 18 selected: false 19 tracksRegLiveness: true 20 registers: 21 - { id: 0, class: sgpr_64 } 22 - { id: 1, class: sreg_32_xm0 } 23 - { id: 2, class: sgpr_32 } 24 - { id: 3, class: vgpr_32 } 25 - { id: 4, class: sreg_64_xexec } 26 - { id: 5, class: sreg_64_xexec } 27 - { id: 6, class: sreg_32 } 28 - { id: 7, class: sreg_32 } 29 - { id: 8, class: sreg_32_xm0 } 30 - { id: 9, class: sreg_64_xexec } 31 - { id: 10, class: sreg_32_xm0 } 32 - { id: 11, class: sreg_32_xm0 } 33 - { id: 12, class: sgpr_64 } 34 - { id: 13, class: sgpr_128 } 35 - { id: 14, class: sreg_32_xm0 } 36 - { id: 15, class: sreg_64 } 37 - { id: 16, class: sgpr_128 } 38 - { id: 17, class: vgpr_32 } 39 - { id: 18, class: vreg_64 } 40 - { id: 19, class: vgpr_32 } 41 - { id: 20, class: vreg_64 } 42 - { id: 21, class: sreg_32_xm0 } 43 - { id: 22, class: sreg_32 } 44 - { id: 23, class: sreg_32 } 45 - { id: 24, class: vgpr_32 } 46 - { id: 25, class: vreg_64 } 47 - { id: 26, class: vgpr_32 } 48 - { id: 27, class: vreg_64 } 49 - { id: 28, class: vreg_64 } 50 - { id: 29, class: vgpr_32 } 51 liveins: 52 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } 53 - { reg: '$vgpr0', virtual-reg: '%3' } 54 frameInfo: 55 isFrameAddressTaken: false 56 isReturnAddressTaken: false 57 hasStackMap: false 58 hasPatchPoint: false 59 stackSize: 0 60 offsetAdjustment: 0 61 maxAlignment: 0 62 adjustsStack: false 63 hasCalls: false 64 maxCallFrameSize: 0 65 hasOpaqueSPAdjustment: false 66 hasVAStart: false 67 hasMustTailInVarArgFunc: false 68 body: | 69 bb.0: 70 liveins: $sgpr0_sgpr1, $vgpr0 71 72 %3 = COPY $vgpr0 73 %0 = COPY $sgpr0_sgpr1 74 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 75 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 76 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec 77 %27 = REG_SEQUENCE %3, 1, %26, 2 78 %10 = S_MOV_B32 61440 79 %11 = S_MOV_B32 0 80 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2 81 %13 = REG_SEQUENCE killed %5, 17, %12, 18 82 %28 = V_LSHL_B64 killed %27, 2, implicit $exec 83 %16 = REG_SEQUENCE killed %4, 17, %12, 18 84 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec 85 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec 86 %29, %9 = V_ADD_I32_e64 %19, %17, implicit $exec 87 %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec 88 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec 89 S_ENDPGM 90 91 ... 92 --- 93 # GCN-LABEL: name: shrink_sub_vop3{{$}} 94 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, implicit $exec 95 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec 96 97 name: shrink_sub_vop3 98 alignment: 0 99 exposesReturnsTwice: false 100 legalized: false 101 regBankSelected: false 102 selected: false 103 tracksRegLiveness: true 104 registers: 105 - { id: 0, class: sgpr_64 } 106 - { id: 1, class: sreg_32_xm0 } 107 - { id: 2, class: sgpr_32 } 108 - { id: 3, class: vgpr_32 } 109 - { id: 4, class: sreg_64_xexec } 110 - { id: 5, class: sreg_64_xexec } 111 - { id: 6, class: sreg_32 } 112 - { id: 7, class: sreg_32 } 113 - { id: 8, class: sreg_32_xm0 } 114 - { id: 9, class: sreg_64_xexec } 115 - { id: 10, class: sreg_32_xm0 } 116 - { id: 11, class: sreg_32_xm0 } 117 - { id: 12, class: sgpr_64 } 118 - { id: 13, class: sgpr_128 } 119 - { id: 14, class: sreg_32_xm0 } 120 - { id: 15, class: sreg_64 } 121 - { id: 16, class: sgpr_128 } 122 - { id: 17, class: vgpr_32 } 123 - { id: 18, class: vreg_64 } 124 - { id: 19, class: vgpr_32 } 125 - { id: 20, class: vreg_64 } 126 - { id: 21, class: sreg_32_xm0 } 127 - { id: 22, class: sreg_32 } 128 - { id: 23, class: sreg_32 } 129 - { id: 24, class: vgpr_32 } 130 - { id: 25, class: vreg_64 } 131 - { id: 26, class: vgpr_32 } 132 - { id: 27, class: vreg_64 } 133 - { id: 28, class: vreg_64 } 134 - { id: 29, class: vgpr_32 } 135 liveins: 136 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } 137 - { reg: '$vgpr0', virtual-reg: '%3' } 138 frameInfo: 139 isFrameAddressTaken: false 140 isReturnAddressTaken: false 141 hasStackMap: false 142 hasPatchPoint: false 143 stackSize: 0 144 offsetAdjustment: 0 145 maxAlignment: 0 146 adjustsStack: false 147 hasCalls: false 148 maxCallFrameSize: 0 149 hasOpaqueSPAdjustment: false 150 hasVAStart: false 151 hasMustTailInVarArgFunc: false 152 body: | 153 bb.0: 154 liveins: $sgpr0_sgpr1, $vgpr0 155 156 %3 = COPY $vgpr0 157 %0 = COPY $sgpr0_sgpr1 158 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 159 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 160 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec 161 %27 = REG_SEQUENCE %3, 1, %26, 2 162 %10 = S_MOV_B32 61440 163 %11 = S_MOV_B32 0 164 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2 165 %13 = REG_SEQUENCE killed %5, 17, %12, 18 166 %28 = V_LSHL_B64 killed %27, 2, implicit $exec 167 %16 = REG_SEQUENCE killed %4, 17, %12, 18 168 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec 169 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec 170 %29, %9 = V_SUB_I32_e64 %19, %17, implicit $exec 171 %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec 172 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec 173 S_ENDPGM 174 175 ... 176 --- 177 # GCN-LABEL: name: shrink_subrev_vop3{{$}} 178 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, implicit $exec 179 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec 180 181 name: shrink_subrev_vop3 182 alignment: 0 183 exposesReturnsTwice: false 184 legalized: false 185 regBankSelected: false 186 selected: false 187 tracksRegLiveness: true 188 registers: 189 - { id: 0, class: sgpr_64 } 190 - { id: 1, class: sreg_32_xm0 } 191 - { id: 2, class: sgpr_32 } 192 - { id: 3, class: vgpr_32 } 193 - { id: 4, class: sreg_64_xexec } 194 - { id: 5, class: sreg_64_xexec } 195 - { id: 6, class: sreg_32 } 196 - { id: 7, class: sreg_32 } 197 - { id: 8, class: sreg_32_xm0 } 198 - { id: 9, class: sreg_64_xexec } 199 - { id: 10, class: sreg_32_xm0 } 200 - { id: 11, class: sreg_32_xm0 } 201 - { id: 12, class: sgpr_64 } 202 - { id: 13, class: sgpr_128 } 203 - { id: 14, class: sreg_32_xm0 } 204 - { id: 15, class: sreg_64 } 205 - { id: 16, class: sgpr_128 } 206 - { id: 17, class: vgpr_32 } 207 - { id: 18, class: vreg_64 } 208 - { id: 19, class: vgpr_32 } 209 - { id: 20, class: vreg_64 } 210 - { id: 21, class: sreg_32_xm0 } 211 - { id: 22, class: sreg_32 } 212 - { id: 23, class: sreg_32 } 213 - { id: 24, class: vgpr_32 } 214 - { id: 25, class: vreg_64 } 215 - { id: 26, class: vgpr_32 } 216 - { id: 27, class: vreg_64 } 217 - { id: 28, class: vreg_64 } 218 - { id: 29, class: vgpr_32 } 219 liveins: 220 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } 221 - { reg: '$vgpr0', virtual-reg: '%3' } 222 frameInfo: 223 isFrameAddressTaken: false 224 isReturnAddressTaken: false 225 hasStackMap: false 226 hasPatchPoint: false 227 stackSize: 0 228 offsetAdjustment: 0 229 maxAlignment: 0 230 adjustsStack: false 231 hasCalls: false 232 maxCallFrameSize: 0 233 hasOpaqueSPAdjustment: false 234 hasVAStart: false 235 hasMustTailInVarArgFunc: false 236 body: | 237 bb.0: 238 liveins: $sgpr0_sgpr1, $vgpr0 239 240 %3 = COPY $vgpr0 241 %0 = COPY $sgpr0_sgpr1 242 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 243 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 244 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec 245 %27 = REG_SEQUENCE %3, 1, %26, 2 246 %10 = S_MOV_B32 61440 247 %11 = S_MOV_B32 0 248 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2 249 %13 = REG_SEQUENCE killed %5, 17, %12, 18 250 %28 = V_LSHL_B64 killed %27, 2, implicit $exec 251 %16 = REG_SEQUENCE killed %4, 17, %12, 18 252 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec 253 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec 254 %29, %9 = V_SUBREV_I32_e64 %19, %17, implicit $exec 255 %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec 256 BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec 257 S_ENDPGM 258 259 ... 260 --- 261 # GCN-LABEL: name: check_addc_src2_vop3{{$}} 262 # GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, implicit $exec 263 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec 264 name: check_addc_src2_vop3 265 alignment: 0 266 exposesReturnsTwice: false 267 legalized: false 268 regBankSelected: false 269 selected: false 270 tracksRegLiveness: true 271 registers: 272 - { id: 0, class: sgpr_64 } 273 - { id: 1, class: sreg_32_xm0 } 274 - { id: 2, class: sgpr_32 } 275 - { id: 3, class: vgpr_32 } 276 - { id: 4, class: sreg_64_xexec } 277 - { id: 5, class: sreg_64_xexec } 278 - { id: 6, class: sreg_32 } 279 - { id: 7, class: sreg_32 } 280 - { id: 8, class: sreg_32_xm0 } 281 - { id: 9, class: sreg_64_xexec } 282 - { id: 10, class: sreg_32_xm0 } 283 - { id: 11, class: sreg_32_xm0 } 284 - { id: 12, class: sgpr_64 } 285 - { id: 13, class: sgpr_128 } 286 - { id: 14, class: sreg_32_xm0 } 287 - { id: 15, class: sreg_64 } 288 - { id: 16, class: sgpr_128 } 289 - { id: 17, class: vgpr_32 } 290 - { id: 18, class: vreg_64 } 291 - { id: 19, class: vgpr_32 } 292 - { id: 20, class: vreg_64 } 293 - { id: 21, class: sreg_32_xm0 } 294 - { id: 22, class: sreg_32 } 295 - { id: 23, class: sreg_32 } 296 - { id: 24, class: vgpr_32 } 297 - { id: 25, class: vreg_64 } 298 - { id: 26, class: vgpr_32 } 299 - { id: 27, class: vreg_64 } 300 - { id: 28, class: vreg_64 } 301 - { id: 29, class: vgpr_32 } 302 liveins: 303 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } 304 - { reg: '$vgpr0', virtual-reg: '%3' } 305 frameInfo: 306 isFrameAddressTaken: false 307 isReturnAddressTaken: false 308 hasStackMap: false 309 hasPatchPoint: false 310 stackSize: 0 311 offsetAdjustment: 0 312 maxAlignment: 0 313 adjustsStack: false 314 hasCalls: false 315 maxCallFrameSize: 0 316 hasOpaqueSPAdjustment: false 317 hasVAStart: false 318 hasMustTailInVarArgFunc: false 319 body: | 320 bb.0: 321 liveins: $sgpr0_sgpr1, $vgpr0 322 323 %3 = COPY $vgpr0 324 %0 = COPY $sgpr0_sgpr1 325 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 326 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 327 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec 328 %27 = REG_SEQUENCE %3, 1, %26, 2 329 %10 = S_MOV_B32 61440 330 %11 = S_MOV_B32 0 331 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2 332 %13 = REG_SEQUENCE killed %5, 17, %12, 18 333 %28 = V_LSHL_B64 killed %27, 2, implicit $exec 334 %16 = REG_SEQUENCE killed %4, 17, %12, 18 335 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec 336 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec 337 %9 = S_MOV_B64 0 338 %29, $vcc = V_ADDC_U32_e64 %19, %17, %9, implicit $exec 339 %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec 340 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec 341 S_ENDPGM 342 343 ... 344 --- 345 # GCN-LABEL: name: shrink_addc_vop3{{$}} 346 # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec 347 # GCN %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec 348 349 name: shrink_addc_vop3 350 alignment: 0 351 exposesReturnsTwice: false 352 legalized: false 353 regBankSelected: false 354 selected: false 355 tracksRegLiveness: true 356 registers: 357 - { id: 0, class: sgpr_64 } 358 - { id: 1, class: sreg_32_xm0 } 359 - { id: 2, class: sgpr_32 } 360 - { id: 3, class: vgpr_32 } 361 - { id: 4, class: sreg_64_xexec } 362 - { id: 5, class: sreg_64_xexec } 363 - { id: 6, class: sreg_32 } 364 - { id: 7, class: sreg_32 } 365 - { id: 8, class: sreg_32_xm0 } 366 - { id: 9, class: sreg_64 } 367 - { id: 10, class: sreg_32_xm0 } 368 - { id: 11, class: sreg_32_xm0 } 369 - { id: 12, class: sgpr_64 } 370 - { id: 13, class: sgpr_128 } 371 - { id: 14, class: sreg_32_xm0 } 372 - { id: 15, class: sreg_64 } 373 - { id: 16, class: sgpr_128 } 374 - { id: 17, class: vgpr_32 } 375 - { id: 18, class: vreg_64 } 376 - { id: 19, class: vgpr_32 } 377 - { id: 20, class: vreg_64 } 378 - { id: 21, class: sreg_32_xm0 } 379 - { id: 22, class: sreg_32 } 380 - { id: 23, class: sreg_32 } 381 - { id: 24, class: vgpr_32 } 382 - { id: 25, class: vreg_64 } 383 - { id: 26, class: vgpr_32 } 384 - { id: 27, class: vreg_64 } 385 - { id: 28, class: vreg_64 } 386 - { id: 29, class: vgpr_32 } 387 liveins: 388 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } 389 - { reg: '$vgpr0', virtual-reg: '%3' } 390 frameInfo: 391 isFrameAddressTaken: false 392 isReturnAddressTaken: false 393 hasStackMap: false 394 hasPatchPoint: false 395 stackSize: 0 396 offsetAdjustment: 0 397 maxAlignment: 0 398 adjustsStack: false 399 hasCalls: false 400 maxCallFrameSize: 0 401 hasOpaqueSPAdjustment: false 402 hasVAStart: false 403 hasMustTailInVarArgFunc: false 404 body: | 405 bb.0: 406 liveins: $sgpr0_sgpr1, $vgpr0 407 408 %3 = COPY $vgpr0 409 %0 = COPY $sgpr0_sgpr1 410 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 411 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 412 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec 413 %27 = REG_SEQUENCE %3, 1, %26, 2 414 %10 = S_MOV_B32 61440 415 %11 = S_MOV_B32 0 416 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2 417 %13 = REG_SEQUENCE killed %5, 17, %12, 18 418 %28 = V_LSHL_B64 killed %27, 2, implicit $exec 419 %16 = REG_SEQUENCE killed %4, 17, %12, 18 420 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec 421 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec 422 $vcc = S_MOV_B64 0 423 %29, $vcc = V_ADDC_U32_e64 %19, %17, $vcc, implicit $exec 424 %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec 425 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec 426 S_ENDPGM 427 428 ... 429 430 --- 431 # GCN-LABEL: name: shrink_addc_undef_vcc{{$}} 432 # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec 433 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec 434 name: shrink_addc_undef_vcc 435 alignment: 0 436 exposesReturnsTwice: false 437 legalized: false 438 regBankSelected: false 439 selected: false 440 tracksRegLiveness: true 441 registers: 442 - { id: 0, class: sgpr_64 } 443 - { id: 1, class: sreg_32_xm0 } 444 - { id: 2, class: sgpr_32 } 445 - { id: 3, class: vgpr_32 } 446 - { id: 4, class: sreg_64_xexec } 447 - { id: 5, class: sreg_64_xexec } 448 - { id: 6, class: sreg_32 } 449 - { id: 7, class: sreg_32 } 450 - { id: 8, class: sreg_32_xm0 } 451 - { id: 9, class: sreg_64 } 452 - { id: 10, class: sreg_32_xm0 } 453 - { id: 11, class: sreg_32_xm0 } 454 - { id: 12, class: sgpr_64 } 455 - { id: 13, class: sgpr_128 } 456 - { id: 14, class: sreg_32_xm0 } 457 - { id: 15, class: sreg_64 } 458 - { id: 16, class: sgpr_128 } 459 - { id: 17, class: vgpr_32 } 460 - { id: 18, class: vreg_64 } 461 - { id: 19, class: vgpr_32 } 462 - { id: 20, class: vreg_64 } 463 - { id: 21, class: sreg_32_xm0 } 464 - { id: 22, class: sreg_32 } 465 - { id: 23, class: sreg_32 } 466 - { id: 24, class: vgpr_32 } 467 - { id: 25, class: vreg_64 } 468 - { id: 26, class: vgpr_32 } 469 - { id: 27, class: vreg_64 } 470 - { id: 28, class: vreg_64 } 471 - { id: 29, class: vgpr_32 } 472 liveins: 473 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' } 474 - { reg: '$vgpr0', virtual-reg: '%3' } 475 frameInfo: 476 isFrameAddressTaken: false 477 isReturnAddressTaken: false 478 hasStackMap: false 479 hasPatchPoint: false 480 stackSize: 0 481 offsetAdjustment: 0 482 maxAlignment: 0 483 adjustsStack: false 484 hasCalls: false 485 maxCallFrameSize: 0 486 hasOpaqueSPAdjustment: false 487 hasVAStart: false 488 hasMustTailInVarArgFunc: false 489 body: | 490 bb.0: 491 liveins: $sgpr0_sgpr1, $vgpr0 492 493 %3 = COPY $vgpr0 494 %0 = COPY $sgpr0_sgpr1 495 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 496 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 497 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec 498 %27 = REG_SEQUENCE %3, 1, %26, 2 499 %10 = S_MOV_B32 61440 500 %11 = S_MOV_B32 0 501 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2 502 %13 = REG_SEQUENCE killed %5, 17, %12, 18 503 %28 = V_LSHL_B64 killed %27, 2, implicit $exec 504 %16 = REG_SEQUENCE killed %4, 17, %12, 18 505 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec 506 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec 507 %29, $vcc = V_ADDC_U32_e64 %19, %17, undef $vcc, implicit $exec 508 %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec 509 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec 510 S_ENDPGM 511 512 ... 513
