1 ; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s 2 ; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s 3 ; 4 ; There is something about Tonga that causes this test to spend a lot of time 5 ; in the default register allocator. 6 7 8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR 9 ; is used to calculate the scratch load/store address. Make sure that this 10 ; mechanism works even when many spills happen. 11 12 ; Just test that it compiles successfully. 13 ; CHECK-LABEL: test 14 define amdgpu_kernel void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) { 15 entry: 16 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 17 %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 18 19 %aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid 20 %a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr 21 22 ; mark most VGPR registers as used to increase register pressure 23 call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" () 24 call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" () 25 call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" () 26 call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" () 27 call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" () 28 call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" () 29 call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" () 30 31 %outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid 32 store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr 33 34 ret void 35 } 36 37 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 38 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 39 40 attributes #1 = { nounwind readnone } 41
