1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2 3 declare i32 @llvm.amdgcn.workitem.id.x() readnone 4 5 ; This is broken because the low half of the 64-bit add remains on the 6 ; SALU, but the upper half does not. The addc expects the carry bit 7 ; set in vcc, which is undefined since the low scalar half add sets 8 ; scc instead. 9 10 ; FIXME: SIShrinkInstructions should force immediate fold. 11 12 ; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_0: 13 ; SI: s_movk_i32 [[K:s[0-9]+]], 0x18f 14 ; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, [[K]], v{{[0-9]+}} 15 ; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 16 define amdgpu_kernel void @imp_def_vcc_split_i64_add_0(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %s.val) { 17 %v.val = load volatile i32, i32 addrspace(1)* %in 18 %vec.0 = insertelement <2 x i32> undef, i32 %s.val, i32 0 19 %vec.1 = insertelement <2 x i32> %vec.0, i32 %v.val, i32 1 20 %bc = bitcast <2 x i32> %vec.1 to i64 21 %add = add i64 %bc, 399 22 store i64 %add, i64 addrspace(1)* %out, align 8 23 ret void 24 } 25 26 ; FUNC-LABEL: {{^}}s_imp_def_vcc_split_i64_add_0: 27 ; SI: s_add_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x18f 28 ; SI: s_addc_u32 {{s[0-9]+}}, 0xf423f, 0 29 define amdgpu_kernel void @s_imp_def_vcc_split_i64_add_0(i64 addrspace(1)* %out, i32 %val) { 30 %vec.0 = insertelement <2 x i32> undef, i32 %val, i32 0 31 %vec.1 = insertelement <2 x i32> %vec.0, i32 999999, i32 1 32 %bc = bitcast <2 x i32> %vec.1 to i64 33 %add = add i64 %bc, 399 34 store i64 %add, i64 addrspace(1)* %out, align 8 35 ret void 36 } 37 38 ; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_1: 39 ; SI: v_add_i32 40 ; SI: v_addc_u32 41 define amdgpu_kernel void @imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) { 42 %v.val = load volatile i32, i32 addrspace(1)* %in 43 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 44 %vec.1 = insertelement <2 x i32> %vec.0, i32 %v.val, i32 1 45 %bc = bitcast <2 x i32> %vec.1 to i64 46 %add = add i64 %bc, %val1 47 store i64 %add, i64 addrspace(1)* %out, align 8 48 ret void 49 } 50 51 ; FUNC-LABEL: {{^}}s_imp_def_vcc_split_i64_add_1: 52 ; SI: s_add_u32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 53 ; SI: s_addc_u32 {{s[0-9]+}}, 0x1869f, {{s[0-9]+}} 54 define amdgpu_kernel void @s_imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 %val0, i64 %val1) { 55 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 56 %vec.1 = insertelement <2 x i32> %vec.0, i32 99999, i32 1 57 %bc = bitcast <2 x i32> %vec.1 to i64 58 %add = add i64 %bc, %val1 59 store i64 %add, i64 addrspace(1)* %out, align 8 60 ret void 61 } 62 63 ; Doesn't use constants 64 ; FUNC-LABEL: {{^}}imp_def_vcc_split_i64_add_2: 65 ; SI: v_add_i32_e32 {{v[0-9]+}}, vcc, {{s[0-9]+}}, {{v[0-9]+}} 66 ; SI: v_addc_u32_e32 {{v[0-9]+}}, vcc, {{v[0-9]+}}, {{v[0-9]+}}, vcc 67 define amdgpu_kernel void @imp_def_vcc_split_i64_add_2(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) { 68 %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone 69 %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 70 %load = load i32, i32 addrspace(1)* %gep 71 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 72 %vec.1 = insertelement <2 x i32> %vec.0, i32 %load, i32 1 73 %bc = bitcast <2 x i32> %vec.1 to i64 74 %add = add i64 %bc, %val1 75 store i64 %add, i64 addrspace(1)* %out, align 8 76 ret void 77 } 78
