1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 3 ; FIXME: Move this to sgpr-copy.ll when this is fixed on VI. 4 ; Make sure that when we split an smrd instruction in order to move it to 5 ; the VALU, we are also moving its users to the VALU. 6 7 ; GCN-LABEL: {{^}}split_smrd_add_worklist: 8 ; GCN: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 9 define amdgpu_ps void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(4)* byval %arg) #0 { 10 bb: 11 %tmp = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 96) 12 %tmp1 = bitcast float %tmp to i32 13 br i1 undef, label %bb2, label %bb3 14 15 bb2: ; preds = %bb 16 unreachable 17 18 bb3: ; preds = %bb 19 %tmp4 = bitcast float %tmp to i32 20 %tmp5 = add i32 %tmp4, 4 21 %tmp6 = sext i32 %tmp5 to i64 22 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(4)* %arg, i64 0, i64 %tmp6 23 %tmp8 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp7, align 32, !tbaa !0 24 %tmp9 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float bitcast (i32 1061158912 to float), float bitcast (i32 1048576000 to float), <8 x i32> %tmp8, <4 x i32> undef, i1 0, i32 0, i32 0) 25 %tmp10 = extractelement <4 x float> %tmp9, i32 0 26 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) 27 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 28 ret void 29 } 30 31 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 32 declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0 33 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 34 declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1 35 36 attributes #0 = { nounwind } 37 attributes #1 = { nounwind readnone } 38 attributes #2 = { nounwind readonly } 39 40 !0 = !{!1, !1, i64 0, i32 1} 41 !1 = !{!"const", !2} 42 !2 = !{!"tbaa root"} 43
