1 ; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s 3 4 ; GCN-LABEL:{{^}}row_filter_C1_D0: 5 define amdgpu_kernel void @row_filter_C1_D0() #0 { 6 entry: 7 br i1 undef, label %for.inc.1, label %do.body.preheader 8 9 do.body.preheader: ; preds = %entry 10 %tmp = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1 11 br i1 undef, label %do.body56.1, label %do.body90 12 13 do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader 14 %tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ %tmp, %do.body.preheader ] 15 %tmp2 = insertelement <4 x i32> %tmp1, i32 undef, i32 2 16 %tmp3 = insertelement <4 x i32> %tmp2, i32 undef, i32 3 17 br i1 undef, label %do.body124.1, label %do.body.1562.preheader 18 19 do.body.1562.preheader: ; preds = %do.body124.1, %do.body90 20 %storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ] 21 %tmp4 = insertelement <4 x i32> undef, i32 undef, i32 1 22 br label %for.inc.1 23 24 do.body56.1: ; preds = %do.body.preheader 25 %tmp5 = insertelement <4 x i32> %tmp, i32 undef, i32 1 26 %or.cond472.1 = or i1 undef, undef 27 br i1 %or.cond472.1, label %do.body56.2, label %do.body90 28 29 do.body56.2: ; preds = %do.body56.1 30 %tmp6 = insertelement <4 x i32> %tmp5, i32 undef, i32 1 31 br label %do.body90 32 33 do.body124.1: ; preds = %do.body90 34 %tmp7 = insertelement <4 x i32> %tmp3, i32 undef, i32 3 35 br label %do.body.1562.preheader 36 37 for.inc.1: ; preds = %do.body.1562.preheader, %entry 38 %storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, %do.body.1562.preheader ] 39 %add.i495 = add <4 x i32> %storemerge591, undef 40 unreachable 41 } 42 43 ; GCN-LABEL: {{^}}foo: 44 ; GCN: s_endpgm 45 define amdgpu_ps void @foo() #0 { 46 bb: 47 br i1 undef, label %bb2, label %bb1 48 49 bb1: ; preds = %bb 50 br i1 undef, label %bb4, label %bb6 51 52 bb2: ; preds = %bb4, %bb 53 %tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ] 54 br i1 undef, label %bb9, label %bb13 55 56 bb4: ; preds = %bb7, %bb6, %bb1 57 %tmp5 = phi float [ undef, %bb1 ], [ undef, %bb6 ], [ %tmp8, %bb7 ] 58 br label %bb2 59 60 bb6: ; preds = %bb1 61 br i1 undef, label %bb7, label %bb4 62 63 bb7: ; preds = %bb6 64 %tmp8 = fmul float undef, undef 65 br label %bb4 66 67 bb9: ; preds = %bb2 68 %tmp10 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) 69 %tmp11 = extractelement <4 x float> %tmp10, i32 1 70 %tmp12 = extractelement <4 x float> %tmp10, i32 3 71 br label %bb14 72 73 bb13: ; preds = %bb2 74 br i1 undef, label %bb23, label %bb24 75 76 bb14: ; preds = %bb27, %bb24, %bb9 77 %tmp15 = phi float [ %tmp12, %bb9 ], [ undef, %bb27 ], [ 0.000000e+00, %bb24 ] 78 %tmp16 = phi float [ %tmp11, %bb9 ], [ undef, %bb27 ], [ %tmp25, %bb24 ] 79 %tmp17 = fmul float 1.050000e+01, %tmp16 80 %tmp18 = fmul float 1.150000e+01, %tmp15 81 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp18, float %tmp17, float %tmp17, float %tmp17, i1 true, i1 true) #0 82 ret void 83 84 bb23: ; preds = %bb13 85 br i1 undef, label %bb24, label %bb26 86 87 bb24: ; preds = %bb26, %bb23, %bb13 88 %tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ] 89 br i1 undef, label %bb27, label %bb14 90 91 bb26: ; preds = %bb23 92 br label %bb24 93 94 bb27: ; preds = %bb24 95 br label %bb14 96 } 97 98 99 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 100 declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 101 102 attributes #0 = { nounwind } 103 attributes #1 = { nounwind readonly } 104
