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      1 # RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
      2 # REQUIRES: asserts
      3 
      4 # CHECK: INTERVALS
      5 # CHECK: %0
      6 # CHECK-LABEL: Machine code for function test0:
      7 
      8 # CHECK: INTERVALS
      9 # CHECK: %0
     10 # CHECK-LABEL: Machine code for function test1:
     11 
     12 --- |
     13   define amdgpu_kernel void @test0() { ret void }
     14   define amdgpu_kernel void @test1() { ret void }
     15 ...
     16 ---
     17 name: test0
     18 registers:
     19   - { id: 0, class: sreg_64 }
     20 body: |
     21   bb.0:
     22     S_NOP 0, implicit-def %0
     23     S_NOP 0, implicit %0
     24 
     25     S_NOP 0, implicit-def undef %0.sub0
     26     S_NOP 0, implicit %0
     27 ...
     28 ---
     29 name: test1
     30 registers:
     31   - { id: 0, class: sreg_64 }
     32 body: |
     33   bb.0:
     34     S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
     35     S_BRANCH %bb.2
     36 
     37   bb.1:
     38     S_NOP 0, implicit-def undef %0.sub0
     39     S_BRANCH %bb.3
     40 
     41   bb.2:
     42     S_NOP 0, implicit-def %0
     43     S_BRANCH %bb.3
     44 
     45   bb.3:
     46     S_NOP 0
     47     S_NOP 0, implicit %0
     48 ...
     49