1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2 ; We may have subregister live ranges that are undefined on some paths. The 3 ; verifier should not complain about this. 4 5 6 ; CHECK-LABEL: {{^}}func: 7 define amdgpu_kernel void @func() #0 { 8 B0: 9 br i1 undef, label %B1, label %B2 10 11 B1: 12 br label %B2 13 14 B2: 15 %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float undef>, %B0 ] 16 br i1 undef, label %B30.1, label %B30.2 17 18 B30.1: 19 %sub = fsub <4 x float> %v0, undef 20 br label %B30.2 21 22 B30.2: 23 %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ] 24 %ve0 = extractelement <4 x float> %v3, i32 0 25 store float %ve0, float addrspace(3)* undef, align 4 26 ret void 27 } 28 29 ; FIXME: Extra undef subregister copy should be removed before 30 ; overwritten with defined copy 31 ; CHECK-LABEL: {{^}}valley_partially_undef_copy: 32 define amdgpu_ps float @valley_partially_undef_copy() #0 { 33 bb: 34 %tmp = load volatile i32, i32 addrspace(1)* undef, align 4 35 %tmp1 = load volatile i32, i32 addrspace(1)* undef, align 4 36 %tmp2 = insertelement <4 x i32> undef, i32 %tmp1, i32 0 37 %tmp3 = bitcast i32 %tmp1 to float 38 %tmp4 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp3, float %tmp3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) 39 %tmp5 = extractelement <4 x float> %tmp4, i32 0 40 %tmp6 = fmul float %tmp5, undef 41 %tmp7 = fadd float %tmp6, %tmp6 42 %tmp8 = insertelement <4 x i32> %tmp2, i32 %tmp, i32 1 43 store <4 x i32> %tmp8, <4 x i32> addrspace(1)* undef, align 16 44 store float %tmp7, float addrspace(1)* undef, align 4 45 br label %bb9 46 47 bb9: ; preds = %bb9, %bb 48 %tmp10 = icmp eq i32 %tmp, 0 49 br i1 %tmp10, label %bb9, label %bb11 50 51 bb11: ; preds = %bb9 52 store <4 x i32> %tmp2, <4 x i32> addrspace(1)* undef, align 16 53 ret float undef 54 } 55 56 ; FIXME: Should be able to remove the undef copies 57 58 ; CHECK-LABEL: {{^}}partially_undef_copy: 59 ; CHECK: v_mov_b32_e32 v5, 5 60 ; CHECK: v_mov_b32_e32 v6, 6 61 62 ; CHECK: v_mov_b32_e32 v[[OUTPUT_LO:[0-9]+]], v5 63 64 ; Undef copy 65 ; CHECK: v_mov_b32_e32 v1, v6 66 67 ; undef copy 68 ; CHECK: v_mov_b32_e32 v2, v7 69 70 ; CHECK: v_mov_b32_e32 v[[OUTPUT_HI:[0-9]+]], v8 71 ; CHECK: v_mov_b32_e32 v[[OUTPUT_LO]], v6 72 73 ; CHECK: buffer_store_dwordx4 v{{\[}}[[OUTPUT_LO]]:[[OUTPUT_HI]]{{\]}} 74 define amdgpu_kernel void @partially_undef_copy() #0 { 75 %tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"() 76 %tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"() 77 78 %partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0 79 %partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0 80 81 store volatile <4 x i32> %partially.undef.1, <4 x i32> addrspace(1)* undef, align 16 82 tail call void asm sideeffect "v_nop", "v={v[5:8]}"(<4 x i32> %partially.undef.0) 83 ret void 84 } 85 86 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 87 88 attributes #0 = { nounwind } 89 attributes #1 = { nounwind readonly } 90
