1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 2 3 ; These tests are for condition codes that are not supported by the hardware 4 5 ; CHECK-LABEL: {{^}}slt: 6 ; CHECK: LSHR 7 ; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z 8 ; CHECK-NEXT: 5(7.006492e-45) 9 define amdgpu_kernel void @slt(i32 addrspace(1)* %out, i32 %in) { 10 entry: 11 %0 = icmp slt i32 %in, 5 12 %1 = select i1 %0, i32 -1, i32 0 13 store i32 %1, i32 addrspace(1)* %out 14 ret void 15 } 16 17 ; CHECK-LABEL: {{^}}ult_i32: 18 ; CHECK: LSHR 19 ; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z 20 ; CHECK-NEXT: 5(7.006492e-45) 21 define amdgpu_kernel void @ult_i32(i32 addrspace(1)* %out, i32 %in) { 22 entry: 23 %0 = icmp ult i32 %in, 5 24 %1 = select i1 %0, i32 -1, i32 0 25 store i32 %1, i32 addrspace(1)* %out 26 ret void 27 } 28 29 ; CHECK-LABEL: {{^}}ult_float: 30 ; CHECK: SETGE * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x 31 ; CHECK-NEXT: 1084227584(5.000000e+00) 32 ; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.0 33 ; CHECK-NEXT: LSHR * 34 define amdgpu_kernel void @ult_float(float addrspace(1)* %out, float %in) { 35 entry: 36 %0 = fcmp ult float %in, 5.0 37 %1 = select i1 %0, float 1.0, float 0.0 38 store float %1, float addrspace(1)* %out 39 ret void 40 } 41 42 ; CHECK-LABEL: {{^}}ult_float_native: 43 ; CHECK: LSHR 44 ; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}} 45 ; CHECK-NEXT: 1084227584(5.000000e+00) 46 define amdgpu_kernel void @ult_float_native(float addrspace(1)* %out, float %in) { 47 entry: 48 %0 = fcmp ult float %in, 5.0 49 %1 = select i1 %0, float 0.0, float 1.0 50 store float %1, float addrspace(1)* %out 51 ret void 52 } 53 54 ; CHECK-LABEL: {{^}}olt: 55 ; CHECK: LSHR 56 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z 57 ; CHECK-NEXT: 1084227584(5.000000e+00) 58 define amdgpu_kernel void @olt(float addrspace(1)* %out, float %in) { 59 entry: 60 %0 = fcmp olt float %in, 5.0 61 %1 = select i1 %0, float 1.0, float 0.0 62 store float %1, float addrspace(1)* %out 63 ret void 64 } 65 66 ; CHECK-LABEL: {{^}}sle: 67 ; CHECK: LSHR 68 ; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z 69 ; CHECK-NEXT: 6(8.407791e-45) 70 define amdgpu_kernel void @sle(i32 addrspace(1)* %out, i32 %in) { 71 entry: 72 %0 = icmp sle i32 %in, 5 73 %1 = select i1 %0, i32 -1, i32 0 74 store i32 %1, i32 addrspace(1)* %out 75 ret void 76 } 77 78 ; CHECK-LABEL: {{^}}ule_i32: 79 ; CHECK: LSHR 80 ; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z 81 ; CHECK-NEXT: 6(8.407791e-45) 82 define amdgpu_kernel void @ule_i32(i32 addrspace(1)* %out, i32 %in) { 83 entry: 84 %0 = icmp ule i32 %in, 5 85 %1 = select i1 %0, i32 -1, i32 0 86 store i32 %1, i32 addrspace(1)* %out 87 ret void 88 } 89 90 ; CHECK-LABEL: {{^}}ule_float: 91 ; CHECK: SETGT * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x 92 ; CHECK-NEXT: 1084227584(5.000000e+00) 93 ; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.0 94 ; CHECK-NEXT: LSHR * 95 define amdgpu_kernel void @ule_float(float addrspace(1)* %out, float %in) { 96 entry: 97 %0 = fcmp ule float %in, 5.0 98 %1 = select i1 %0, float 1.0, float 0.0 99 store float %1, float addrspace(1)* %out 100 ret void 101 } 102 103 ; CHECK-LABEL: {{^}}ule_float_native: 104 ; CHECK: LSHR 105 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}} 106 ; CHECK-NEXT: 1084227584(5.000000e+00) 107 define amdgpu_kernel void @ule_float_native(float addrspace(1)* %out, float %in) { 108 entry: 109 %0 = fcmp ule float %in, 5.0 110 %1 = select i1 %0, float 0.0, float 1.0 111 store float %1, float addrspace(1)* %out 112 ret void 113 } 114 115 ; CHECK-LABEL: {{^}}ole: 116 ; CHECK: LSHR 117 ; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z 118 ; CHECK-NEXT:1084227584(5.000000e+00) 119 define amdgpu_kernel void @ole(float addrspace(1)* %out, float %in) { 120 entry: 121 %0 = fcmp ole float %in, 5.0 122 %1 = select i1 %0, float 1.0, float 0.0 123 store float %1, float addrspace(1)* %out 124 ret void 125 } 126
