1 # RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 2 --- | 3 define void @test_trunc_and_zext_s1() { ret void } 4 define void @test_trunc_and_sext_s1() { ret void } 5 define void @test_trunc_and_sext_s8() { ret void } 6 define void @test_trunc_and_zext_s16() { ret void } 7 define void @test_trunc_and_anyext_s8() { ret void } 8 define void @test_trunc_and_anyext_s16() { ret void } 9 define void @test_trunc_s64() #0 { ret void } 10 11 define void @test_add_s32() { ret void } 12 define void @test_add_fold_imm_s32() { ret void } 13 define void @test_add_no_fold_imm_s32() #3 { ret void } 14 15 define void @test_fadd_s32() #0 { ret void } 16 define void @test_fadd_s64() #0 { ret void } 17 18 define void @test_fsub_s32() #0 { ret void } 19 define void @test_fsub_s64() #0 { ret void } 20 21 define void @test_fmul_s32() #0 { ret void } 22 define void @test_fmul_s64() #0 { ret void } 23 24 define void @test_fdiv_s32() #0 { ret void } 25 define void @test_fdiv_s64() #0 { ret void } 26 27 define void @test_fneg_s32() #0 { ret void } 28 define void @test_fneg_s64() #0 { ret void } 29 30 define void @test_fma_s32() #4 { ret void } 31 define void @test_fma_s64() #4 { ret void } 32 33 define void @test_fpext_s32_to_s64() #0 { ret void } 34 define void @test_fptrunc_s64_to_s32() #0 {ret void } 35 36 define void @test_fptosi_s32() #0 { ret void } 37 define void @test_fptosi_s64() #0 { ret void } 38 define void @test_fptoui_s32() #0 { ret void } 39 define void @test_fptoui_s64() #0 { ret void } 40 41 define void @test_sitofp_s32() #0 { ret void } 42 define void @test_sitofp_s64() #0 { ret void } 43 define void @test_uitofp_s32() #0 { ret void } 44 define void @test_uitofp_s64() #0 { ret void } 45 46 define void @test_sub_s32() { ret void } 47 define void @test_sub_imm_s32() { ret void } 48 define void @test_sub_rev_imm_s32() { ret void } 49 50 define void @test_mul_s32() #1 { ret void } 51 define void @test_mulv5_s32() { ret void } 52 53 define void @test_sdiv_s32() #2 { ret void } 54 define void @test_udiv_s32() #2 { ret void } 55 56 define void @test_lshr_s32() { ret void } 57 define void @test_ashr_s32() { ret void } 58 define void @test_shl_s32() { ret void } 59 60 define void @test_load_from_stack() { ret void } 61 define void @test_load_f32() #0 { ret void } 62 define void @test_load_f64() #0 { ret void } 63 64 define void @test_stores() #0 { ret void } 65 66 define void @test_gep() { ret void } 67 define void @test_constant_imm() { ret void } 68 define void @test_constant_cimm() { ret void } 69 define void @test_pointer_constant_unconstrained() { ret void } 70 define void @test_pointer_constant_constrained() { ret void } 71 72 define void @test_inttoptr_s32() { ret void } 73 define void @test_ptrtoint_s32() { ret void } 74 75 define void @test_select_s32() { ret void } 76 define void @test_select_ptr() { ret void } 77 78 define void @test_br() { ret void } 79 80 define void @test_phi_s32() { ret void } 81 define void @test_phi_s64() #0 { ret void } 82 83 define void @test_soft_fp_double() #0 { ret void } 84 85 attributes #0 = { "target-features"="+vfp2,-neonfp" } 86 attributes #1 = { "target-features"="+v6" } 87 attributes #2 = { "target-features"="+hwdiv-arm" } 88 attributes #3 = { "target-features"="+v6t2" } 89 attributes #4 = { "target-features"="+vfp4,-neonfp" } 90 ... 91 --- 92 name: test_trunc_and_zext_s1 93 # CHECK-LABEL: name: test_trunc_and_zext_s1 94 legalized: true 95 regBankSelected: true 96 selected: false 97 # CHECK: selected: true 98 registers: 99 - { id: 0, class: gprb } 100 - { id: 1, class: gprb } 101 - { id: 2, class: gprb } 102 body: | 103 bb.0: 104 liveins: $r0 105 106 %0(s32) = COPY $r0 107 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 108 109 %1(s1) = G_TRUNC %0(s32) 110 111 %2(s32) = G_ZEXT %1(s1) 112 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg 113 114 $r0 = COPY %2(s32) 115 ; CHECK: $r0 = COPY [[VREGEXT]] 116 117 BX_RET 14, $noreg, implicit $r0 118 ; CHECK: BX_RET 14, $noreg, implicit $r0 119 ... 120 --- 121 name: test_trunc_and_sext_s1 122 # CHECK-LABEL: name: test_trunc_and_sext_s1 123 legalized: true 124 regBankSelected: true 125 selected: false 126 # CHECK: selected: true 127 registers: 128 - { id: 0, class: gprb } 129 - { id: 1, class: gprb } 130 - { id: 2, class: gprb } 131 body: | 132 bb.0: 133 liveins: $r0 134 135 %0(s32) = COPY $r0 136 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 137 138 %1(s1) = G_TRUNC %0(s32) 139 140 %2(s32) = G_SEXT %1(s1) 141 ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg 142 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg 143 144 $r0 = COPY %2(s32) 145 ; CHECK: $r0 = COPY [[VREGEXT]] 146 147 BX_RET 14, $noreg, implicit $r0 148 ; CHECK: BX_RET 14, $noreg, implicit $r0 149 ... 150 --- 151 name: test_trunc_and_sext_s8 152 # CHECK-LABEL: name: test_trunc_and_sext_s8 153 legalized: true 154 regBankSelected: true 155 selected: false 156 # CHECK: selected: true 157 registers: 158 - { id: 0, class: gprb } 159 - { id: 1, class: gprb } 160 - { id: 2, class: gprb } 161 body: | 162 bb.0: 163 liveins: $r0 164 165 %0(s32) = COPY $r0 166 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 167 168 %1(s8) = G_TRUNC %0(s32) 169 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] 170 171 %2(s32) = G_SEXT %1(s8) 172 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg 173 174 $r0 = COPY %2(s32) 175 ; CHECK: $r0 = COPY [[VREGEXT]] 176 177 BX_RET 14, $noreg, implicit $r0 178 ; CHECK: BX_RET 14, $noreg, implicit $r0 179 ... 180 --- 181 name: test_trunc_and_zext_s16 182 # CHECK-LABEL: name: test_trunc_and_zext_s16 183 legalized: true 184 regBankSelected: true 185 selected: false 186 # CHECK: selected: true 187 registers: 188 - { id: 0, class: gprb } 189 - { id: 1, class: gprb } 190 - { id: 2, class: gprb } 191 body: | 192 bb.0: 193 liveins: $r0 194 195 %0(s32) = COPY $r0 196 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 197 198 %1(s16) = G_TRUNC %0(s32) 199 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] 200 201 %2(s32) = G_ZEXT %1(s16) 202 ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, $noreg 203 204 $r0 = COPY %2(s32) 205 ; CHECK: $r0 = COPY [[VREGEXT]] 206 207 BX_RET 14, $noreg, implicit $r0 208 ; CHECK: BX_RET 14, $noreg, implicit $r0 209 ... 210 --- 211 name: test_trunc_and_anyext_s8 212 # CHECK-LABEL: name: test_trunc_and_anyext_s8 213 legalized: true 214 regBankSelected: true 215 selected: false 216 # CHECK: selected: true 217 registers: 218 - { id: 0, class: gprb } 219 - { id: 1, class: gprb } 220 - { id: 2, class: gprb } 221 body: | 222 bb.0: 223 liveins: $r0 224 225 %0(s32) = COPY $r0 226 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 227 228 %1(s8) = G_TRUNC %0(s32) 229 230 %2(s32) = G_ANYEXT %1(s8) 231 232 $r0 = COPY %2(s32) 233 ; CHECK: $r0 = COPY [[VREG]] 234 235 BX_RET 14, $noreg, implicit $r0 236 ; CHECK: BX_RET 14, $noreg, implicit $r0 237 ... 238 --- 239 name: test_trunc_and_anyext_s16 240 # CHECK-LABEL: name: test_trunc_and_anyext_s16 241 legalized: true 242 regBankSelected: true 243 selected: false 244 # CHECK: selected: true 245 registers: 246 - { id: 0, class: gprb } 247 - { id: 1, class: gprb } 248 - { id: 2, class: gprb } 249 body: | 250 bb.0: 251 liveins: $r0 252 253 %0(s32) = COPY $r0 254 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 255 256 %1(s16) = G_TRUNC %0(s32) 257 258 %2(s32) = G_ANYEXT %1(s16) 259 260 $r0 = COPY %2(s32) 261 ; CHECK: $r0 = COPY [[VREG]] 262 263 BX_RET 14, $noreg, implicit $r0 264 ; CHECK: BX_RET 14, $noreg, implicit $r0 265 ... 266 --- 267 name: test_trunc_s64 268 # CHECK-LABEL: name: test_trunc_s64 269 legalized: true 270 regBankSelected: true 271 selected: false 272 # CHECK: selected: true 273 registers: 274 - { id: 0, class: fprb } 275 - { id: 1, class: gprb } 276 - { id: 2, class: gprb } 277 body: | 278 bb.0: 279 liveins: $r0, $d0 280 281 %0(s64) = COPY $d0 282 ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY $d0 283 284 %2(p0) = COPY $r0 285 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 286 287 %1(s32) = G_TRUNC %0(s64) 288 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]] 289 290 G_STORE %1(s32), %2 :: (store 4) 291 ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, $noreg 292 293 BX_RET 14, $noreg 294 ; CHECK: BX_RET 14, $noreg 295 ... 296 --- 297 name: test_add_s32 298 # CHECK-LABEL: name: test_add_s32 299 legalized: true 300 regBankSelected: true 301 selected: false 302 # CHECK: selected: true 303 registers: 304 - { id: 0, class: gprb } 305 - { id: 1, class: gprb } 306 - { id: 2, class: gprb } 307 body: | 308 bb.0: 309 liveins: $r0, $r1 310 311 %0(s32) = COPY $r0 312 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 313 314 %1(s32) = COPY $r1 315 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 316 317 %2(s32) = G_ADD %0, %1 318 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg 319 320 $r0 = COPY %2(s32) 321 ; CHECK: $r0 = COPY [[VREGSUM]] 322 323 BX_RET 14, $noreg, implicit $r0 324 ; CHECK: BX_RET 14, $noreg, implicit $r0 325 ... 326 --- 327 name: test_add_fold_imm_s32 328 # CHECK-LABEL: name: test_add_fold_imm_s32 329 legalized: true 330 regBankSelected: true 331 selected: false 332 # CHECK: selected: true 333 registers: 334 - { id: 0, class: gprb } 335 - { id: 1, class: gprb } 336 - { id: 2, class: gprb } 337 body: | 338 bb.0: 339 liveins: $r0 340 341 %0(s32) = COPY $r0 342 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 343 344 %1(s32) = G_CONSTANT i32 255 345 %2(s32) = G_ADD %0, %1 346 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, $noreg, $noreg 347 348 $r0 = COPY %2(s32) 349 ; CHECK: $r0 = COPY [[VREGSUM]] 350 351 BX_RET 14, $noreg, implicit $r0 352 ; CHECK: BX_RET 14, $noreg, implicit $r0 353 ... 354 --- 355 name: test_add_no_fold_imm_s32 356 # CHECK-LABEL: name: test_add_no_fold_imm_s32 357 legalized: true 358 regBankSelected: true 359 selected: false 360 # CHECK: selected: true 361 registers: 362 - { id: 0, class: gprb } 363 - { id: 1, class: gprb } 364 - { id: 2, class: gprb } 365 body: | 366 bb.0: 367 liveins: $r0 368 369 %0(s32) = COPY $r0 370 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 371 372 %1(s32) = G_CONSTANT i32 65535 373 ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, $noreg 374 375 %2(s32) = G_ADD %0, %1 376 ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg 377 378 $r0 = COPY %2(s32) 379 ; CHECK: $r0 = COPY [[VREGSUM]] 380 381 BX_RET 14, $noreg, implicit $r0 382 ; CHECK: BX_RET 14, $noreg, implicit $r0 383 ... 384 --- 385 name: test_fadd_s32 386 # CHECK-LABEL: name: test_fadd_s32 387 legalized: true 388 regBankSelected: true 389 selected: false 390 # CHECK: selected: true 391 registers: 392 - { id: 0, class: fprb } 393 - { id: 1, class: fprb } 394 - { id: 2, class: fprb } 395 body: | 396 bb.0: 397 liveins: $s0, $s1 398 399 %0(s32) = COPY $s0 400 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 401 402 %1(s32) = COPY $s1 403 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 404 405 %2(s32) = G_FADD %0, %1 406 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, $noreg 407 408 $s0 = COPY %2(s32) 409 ; CHECK: $s0 = COPY [[VREGSUM]] 410 411 BX_RET 14, $noreg, implicit $s0 412 ; CHECK: BX_RET 14, $noreg, implicit $s0 413 ... 414 --- 415 name: test_fadd_s64 416 # CHECK-LABEL: name: test_fadd_s64 417 legalized: true 418 regBankSelected: true 419 selected: false 420 # CHECK: selected: true 421 registers: 422 - { id: 0, class: fprb } 423 - { id: 1, class: fprb } 424 - { id: 2, class: fprb } 425 body: | 426 bb.0: 427 liveins: $d0, $d1 428 429 %0(s64) = COPY $d0 430 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 431 432 %1(s64) = COPY $d1 433 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 434 435 %2(s64) = G_FADD %0, %1 436 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, $noreg 437 438 $d0 = COPY %2(s64) 439 ; CHECK: $d0 = COPY [[VREGSUM]] 440 441 BX_RET 14, $noreg, implicit $d0 442 ; CHECK: BX_RET 14, $noreg, implicit $d0 443 ... 444 --- 445 name: test_fsub_s32 446 # CHECK-LABEL: name: test_fsub_s32 447 legalized: true 448 regBankSelected: true 449 selected: false 450 # CHECK: selected: true 451 registers: 452 - { id: 0, class: fprb } 453 - { id: 1, class: fprb } 454 - { id: 2, class: fprb } 455 body: | 456 bb.0: 457 liveins: $s0, $s1 458 459 %0(s32) = COPY $s0 460 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 461 462 %1(s32) = COPY $s1 463 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 464 465 %2(s32) = G_FSUB %0, %1 466 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, $noreg 467 468 $s0 = COPY %2(s32) 469 ; CHECK: $s0 = COPY [[VREGSUM]] 470 471 BX_RET 14, $noreg, implicit $s0 472 ; CHECK: BX_RET 14, $noreg, implicit $s0 473 ... 474 --- 475 name: test_fsub_s64 476 # CHECK-LABEL: name: test_fsub_s64 477 legalized: true 478 regBankSelected: true 479 selected: false 480 # CHECK: selected: true 481 registers: 482 - { id: 0, class: fprb } 483 - { id: 1, class: fprb } 484 - { id: 2, class: fprb } 485 body: | 486 bb.0: 487 liveins: $d0, $d1 488 489 %0(s64) = COPY $d0 490 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 491 492 %1(s64) = COPY $d1 493 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 494 495 %2(s64) = G_FSUB %0, %1 496 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, $noreg 497 498 $d0 = COPY %2(s64) 499 ; CHECK: $d0 = COPY [[VREGSUM]] 500 501 BX_RET 14, $noreg, implicit $d0 502 ; CHECK: BX_RET 14, $noreg, implicit $d0 503 ... 504 --- 505 name: test_fmul_s32 506 # CHECK-LABEL: name: test_fmul_s32 507 legalized: true 508 regBankSelected: true 509 selected: false 510 # CHECK: selected: true 511 registers: 512 - { id: 0, class: fprb } 513 - { id: 1, class: fprb } 514 - { id: 2, class: fprb } 515 body: | 516 bb.0: 517 liveins: $s0, $s1 518 519 %0(s32) = COPY $s0 520 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 521 522 %1(s32) = COPY $s1 523 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 524 525 %2(s32) = G_FMUL %0, %1 526 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, $noreg 527 528 $s0 = COPY %2(s32) 529 ; CHECK: $s0 = COPY [[VREGSUM]] 530 531 BX_RET 14, $noreg, implicit $s0 532 ; CHECK: BX_RET 14, $noreg, implicit $s0 533 ... 534 --- 535 name: test_fmul_s64 536 # CHECK-LABEL: name: test_fmul_s64 537 legalized: true 538 regBankSelected: true 539 selected: false 540 # CHECK: selected: true 541 registers: 542 - { id: 0, class: fprb } 543 - { id: 1, class: fprb } 544 - { id: 2, class: fprb } 545 body: | 546 bb.0: 547 liveins: $d0, $d1 548 549 %0(s64) = COPY $d0 550 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 551 552 %1(s64) = COPY $d1 553 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 554 555 %2(s64) = G_FMUL %0, %1 556 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, $noreg 557 558 $d0 = COPY %2(s64) 559 ; CHECK: $d0 = COPY [[VREGSUM]] 560 561 BX_RET 14, $noreg, implicit $d0 562 ; CHECK: BX_RET 14, $noreg, implicit $d0 563 ... 564 --- 565 name: test_fdiv_s32 566 # CHECK-LABEL: name: test_fdiv_s32 567 legalized: true 568 regBankSelected: true 569 selected: false 570 # CHECK: selected: true 571 registers: 572 - { id: 0, class: fprb } 573 - { id: 1, class: fprb } 574 - { id: 2, class: fprb } 575 body: | 576 bb.0: 577 liveins: $s0, $s1 578 579 %0(s32) = COPY $s0 580 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 581 582 %1(s32) = COPY $s1 583 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 584 585 %2(s32) = G_FDIV %0, %1 586 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, $noreg 587 588 $s0 = COPY %2(s32) 589 ; CHECK: $s0 = COPY [[VREGSUM]] 590 591 BX_RET 14, $noreg, implicit $s0 592 ; CHECK: BX_RET 14, $noreg, implicit $s0 593 ... 594 --- 595 name: test_fdiv_s64 596 # CHECK-LABEL: name: test_fdiv_s64 597 legalized: true 598 regBankSelected: true 599 selected: false 600 # CHECK: selected: true 601 registers: 602 - { id: 0, class: fprb } 603 - { id: 1, class: fprb } 604 - { id: 2, class: fprb } 605 body: | 606 bb.0: 607 liveins: $d0, $d1 608 609 %0(s64) = COPY $d0 610 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 611 612 %1(s64) = COPY $d1 613 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 614 615 %2(s64) = G_FDIV %0, %1 616 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, $noreg 617 618 $d0 = COPY %2(s64) 619 ; CHECK: $d0 = COPY [[VREGSUM]] 620 621 BX_RET 14, $noreg, implicit $d0 622 ; CHECK: BX_RET 14, $noreg, implicit $d0 623 ... 624 --- 625 name: test_fneg_s32 626 # CHECK-LABEL: name: test_fneg_s32 627 legalized: true 628 regBankSelected: true 629 selected: false 630 # CHECK: selected: true 631 registers: 632 - { id: 0, class: fprb } 633 - { id: 1, class: fprb } 634 body: | 635 bb.0: 636 liveins: $s0 637 638 %0(s32) = COPY $s0 639 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 640 641 %1(s32) = G_FNEG %0 642 ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, $noreg 643 644 $s0 = COPY %1(s32) 645 ; CHECK: $s0 = COPY [[VREGSUM]] 646 647 BX_RET 14, $noreg, implicit $s0 648 ; CHECK: BX_RET 14, $noreg, implicit $s0 649 ... 650 --- 651 name: test_fneg_s64 652 # CHECK-LABEL: name: test_fneg_s64 653 legalized: true 654 regBankSelected: true 655 selected: false 656 # CHECK: selected: true 657 registers: 658 - { id: 0, class: fprb } 659 - { id: 1, class: fprb } 660 - { id: 2, class: fprb } 661 body: | 662 bb.0: 663 liveins: $d0 664 665 %0(s64) = COPY $d0 666 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 667 668 %1(s64) = G_FNEG %0 669 ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, $noreg 670 671 $d0 = COPY %1(s64) 672 ; CHECK: $d0 = COPY [[VREGSUM]] 673 674 BX_RET 14, $noreg, implicit $d0 675 ; CHECK: BX_RET 14, $noreg, implicit $d0 676 ... 677 --- 678 name: test_fma_s32 679 # CHECK-LABEL: name: test_fma_s32 680 legalized: true 681 regBankSelected: true 682 selected: false 683 # CHECK: selected: true 684 registers: 685 - { id: 0, class: fprb } 686 - { id: 1, class: fprb } 687 - { id: 2, class: fprb } 688 - { id: 3, class: fprb } 689 body: | 690 bb.0: 691 liveins: $s0, $s1, $s2 692 693 %0(s32) = COPY $s0 694 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 695 696 %1(s32) = COPY $s1 697 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 698 699 %2(s32) = COPY $s2 700 ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2 701 702 %3(s32) = G_FMA %0, %1, %2 703 ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg 704 705 $s0 = COPY %3(s32) 706 ; CHECK: $s0 = COPY [[VREGR]] 707 708 BX_RET 14, $noreg, implicit $s0 709 ; CHECK: BX_RET 14, $noreg, implicit $s0 710 ... 711 --- 712 name: test_fma_s64 713 # CHECK-LABEL: name: test_fma_s64 714 legalized: true 715 regBankSelected: true 716 selected: false 717 # CHECK: selected: true 718 registers: 719 - { id: 0, class: fprb } 720 - { id: 1, class: fprb } 721 - { id: 2, class: fprb } 722 - { id: 3, class: fprb } 723 body: | 724 bb.0: 725 liveins: $d0, $d1, $d2 726 727 %0(s64) = COPY $d0 728 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 729 730 %1(s64) = COPY $d1 731 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 732 733 %2(s64) = COPY $d2 734 ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 735 736 %3(s64) = G_FMA %0, %1, %2 737 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg 738 739 $d0 = COPY %3(s64) 740 ; CHECK: $d0 = COPY [[VREGR]] 741 742 BX_RET 14, $noreg, implicit $d0 743 ; CHECK: BX_RET 14, $noreg, implicit $d0 744 ... 745 --- 746 name: test_fpext_s32_to_s64 747 # CHECK-LABEL: name: test_fpext_s32_to_s64 748 legalized: true 749 regBankSelected: true 750 selected: false 751 # CHECK: selected: true 752 registers: 753 - { id: 0, class: fprb } 754 - { id: 1, class: fprb } 755 body: | 756 bb.0: 757 liveins: $s0 758 759 %0(s32) = COPY $s0 760 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 761 762 %1(s64) = G_FPEXT %0(s32) 763 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, $noreg 764 765 $d0 = COPY %1(s64) 766 ; CHECK: $d0 = COPY [[VREGR]] 767 768 BX_RET 14, $noreg, implicit $d0 769 ; CHECK: BX_RET 14, $noreg, implicit $d0 770 ... 771 --- 772 name: test_fptrunc_s64_to_s32 773 # CHECK-LABEL: name: test_fptrunc_s64_to_s32 774 legalized: true 775 regBankSelected: true 776 selected: false 777 # CHECK: selected: true 778 registers: 779 - { id: 0, class: fprb } 780 - { id: 1, class: fprb } 781 body: | 782 bb.0: 783 liveins: $d0 784 785 %0(s64) = COPY $d0 786 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 787 788 %1(s32) = G_FPTRUNC %0(s64) 789 ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, $noreg 790 791 $s0 = COPY %1(s32) 792 ; CHECK: $s0 = COPY [[VREGR]] 793 794 BX_RET 14, $noreg, implicit $s0 795 ; CHECK: BX_RET 14, $noreg, implicit $s0 796 ... 797 --- 798 name: test_fptosi_s32 799 # CHECK-LABEL: name: test_fptosi_s32 800 legalized: true 801 regBankSelected: true 802 selected: false 803 # CHECK: selected: true 804 registers: 805 - { id: 0, class: fprb } 806 - { id: 1, class: gprb } 807 body: | 808 bb.0: 809 liveins: $s0 810 811 %0(s32) = COPY $s0 812 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 813 814 %1(s32) = G_FPTOSI %0(s32) 815 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, $noreg 816 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 817 818 $r0 = COPY %1(s32) 819 ; CHECK: $r0 = COPY [[VREGR]] 820 821 BX_RET 14, $noreg, implicit $r0 822 ; CHECK: BX_RET 14, $noreg, implicit $r0 823 ... 824 --- 825 name: test_fptosi_s64 826 # CHECK-LABEL: name: test_fptosi_s64 827 legalized: true 828 regBankSelected: true 829 selected: false 830 # CHECK: selected: true 831 registers: 832 - { id: 0, class: fprb } 833 - { id: 1, class: gprb } 834 body: | 835 bb.0: 836 liveins: $d0 837 838 %0(s64) = COPY $d0 839 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 840 841 %1(s32) = G_FPTOSI %0(s64) 842 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, $noreg 843 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 844 845 $r0 = COPY %1(s32) 846 ; CHECK: $r0 = COPY [[VREGR]] 847 848 BX_RET 14, $noreg, implicit $r0 849 ; CHECK: BX_RET 14, $noreg, implicit $r0 850 ... 851 --- 852 name: test_fptoui_s32 853 # CHECK-LABEL: name: test_fptoui_s32 854 legalized: true 855 regBankSelected: true 856 selected: false 857 # CHECK: selected: true 858 registers: 859 - { id: 0, class: fprb } 860 - { id: 1, class: gprb } 861 body: | 862 bb.0: 863 liveins: $s0 864 865 %0(s32) = COPY $s0 866 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 867 868 %1(s32) = G_FPTOUI %0(s32) 869 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, $noreg 870 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 871 872 $r0 = COPY %1(s32) 873 ; CHECK: $r0 = COPY [[VREGR]] 874 875 BX_RET 14, $noreg, implicit $r0 876 ; CHECK: BX_RET 14, $noreg, implicit $r0 877 ... 878 --- 879 name: test_fptoui_s64 880 # CHECK-LABEL: name: test_fptoui_s64 881 legalized: true 882 regBankSelected: true 883 selected: false 884 # CHECK: selected: true 885 registers: 886 - { id: 0, class: fprb } 887 - { id: 1, class: gprb } 888 body: | 889 bb.0: 890 liveins: $d0 891 892 %0(s64) = COPY $d0 893 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 894 895 %1(s32) = G_FPTOUI %0(s64) 896 ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, $noreg 897 ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] 898 899 $r0 = COPY %1(s32) 900 ; CHECK: $r0 = COPY [[VREGR]] 901 902 BX_RET 14, $noreg, implicit $r0 903 ; CHECK: BX_RET 14, $noreg, implicit $r0 904 ... 905 --- 906 name: test_sitofp_s32 907 # CHECK-LABEL: name: test_sitofp_s32 908 legalized: true 909 regBankSelected: true 910 selected: false 911 # CHECK: selected: true 912 registers: 913 - { id: 0, class: gprb } 914 - { id: 1, class: fprb } 915 body: | 916 bb.0: 917 liveins: $r0 918 919 %0(s32) = COPY $r0 920 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 921 922 %1(s32) = G_SITOFP %0(s32) 923 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 924 ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, $noreg 925 926 $s0 = COPY %1(s32) 927 ; CHECK: $s0 = COPY [[VREGR]] 928 929 BX_RET 14, $noreg, implicit $s0 930 ; CHECK: BX_RET 14, $noreg, implicit $s0 931 ... 932 --- 933 name: test_sitofp_s64 934 # CHECK-LABEL: name: test_sitofp_s64 935 legalized: true 936 regBankSelected: true 937 selected: false 938 # CHECK: selected: true 939 registers: 940 - { id: 0, class: gprb } 941 - { id: 1, class: fprb } 942 body: | 943 bb.0: 944 liveins: $r0 945 946 %0(s32) = COPY $r0 947 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 948 949 %1(s64) = G_SITOFP %0(s32) 950 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 951 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, $noreg 952 953 $d0 = COPY %1(s64) 954 ; CHECK: $d0 = COPY [[VREGR]] 955 956 BX_RET 14, $noreg, implicit $d0 957 ; CHECK: BX_RET 14, $noreg, implicit $d0 958 ... 959 --- 960 name: test_uitofp_s32 961 # CHECK-LABEL: name: test_uitofp_s32 962 legalized: true 963 regBankSelected: true 964 selected: false 965 # CHECK: selected: true 966 registers: 967 - { id: 0, class: gprb } 968 - { id: 1, class: fprb } 969 body: | 970 bb.0: 971 liveins: $r0 972 973 %0(s32) = COPY $r0 974 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 975 976 %1(s32) = G_UITOFP %0(s32) 977 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 978 ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, $noreg 979 980 $s0 = COPY %1(s32) 981 ; CHECK: $s0 = COPY [[VREGR]] 982 983 BX_RET 14, $noreg, implicit $s0 984 ; CHECK: BX_RET 14, $noreg, implicit $s0 985 ... 986 --- 987 name: test_uitofp_s64 988 # CHECK-LABEL: name: test_uitofp_s64 989 legalized: true 990 regBankSelected: true 991 selected: false 992 # CHECK: selected: true 993 registers: 994 - { id: 0, class: gprb } 995 - { id: 1, class: fprb } 996 body: | 997 bb.0: 998 liveins: $r0 999 1000 %0(s32) = COPY $r0 1001 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1002 1003 %1(s64) = G_UITOFP %0(s32) 1004 ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] 1005 ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, $noreg 1006 1007 $d0 = COPY %1(s64) 1008 ; CHECK: $d0 = COPY [[VREGR]] 1009 1010 BX_RET 14, $noreg, implicit $d0 1011 ; CHECK: BX_RET 14, $noreg, implicit $d0 1012 ... 1013 --- 1014 name: test_sub_s32 1015 # CHECK-LABEL: name: test_sub_s32 1016 legalized: true 1017 regBankSelected: true 1018 selected: false 1019 # CHECK: selected: true 1020 registers: 1021 - { id: 0, class: gprb } 1022 - { id: 1, class: gprb } 1023 - { id: 2, class: gprb } 1024 body: | 1025 bb.0: 1026 liveins: $r0, $r1 1027 1028 %0(s32) = COPY $r0 1029 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1030 1031 %1(s32) = COPY $r1 1032 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1033 1034 %2(s32) = G_SUB %0, %1 1035 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg 1036 1037 $r0 = COPY %2(s32) 1038 ; CHECK: $r0 = COPY [[VREGRES]] 1039 1040 BX_RET 14, $noreg, implicit $r0 1041 ; CHECK: BX_RET 14, $noreg, implicit $r0 1042 ... 1043 --- 1044 name: test_sub_imm_s32 1045 # CHECK-LABEL: name: test_sub_imm_s32 1046 legalized: true 1047 regBankSelected: true 1048 selected: false 1049 # CHECK: selected: true 1050 registers: 1051 - { id: 0, class: gprb } 1052 - { id: 1, class: gprb } 1053 - { id: 2, class: gprb } 1054 body: | 1055 bb.0: 1056 liveins: $r0, $r1 1057 1058 %0(s32) = COPY $r0 1059 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1060 1061 %1(s32) = G_CONSTANT i32 17 1062 %2(s32) = G_SUB %0, %1 1063 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, $noreg, $noreg 1064 1065 $r0 = COPY %2(s32) 1066 ; CHECK: $r0 = COPY [[VREGRES]] 1067 1068 BX_RET 14, $noreg, implicit $r0 1069 ; CHECK: BX_RET 14, $noreg, implicit $r0 1070 ... 1071 --- 1072 name: test_sub_rev_imm_s32 1073 # CHECK-LABEL: name: test_sub_rev_imm_s32 1074 legalized: true 1075 regBankSelected: true 1076 selected: false 1077 # CHECK: selected: true 1078 registers: 1079 - { id: 0, class: gprb } 1080 - { id: 1, class: gprb } 1081 - { id: 2, class: gprb } 1082 body: | 1083 bb.0: 1084 liveins: $r0, $r1 1085 1086 %0(s32) = COPY $r0 1087 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1088 1089 %1(s32) = G_CONSTANT i32 17 1090 %2(s32) = G_SUB %1, %0 1091 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, $noreg, $noreg 1092 1093 $r0 = COPY %2(s32) 1094 ; CHECK: $r0 = COPY [[VREGRES]] 1095 1096 BX_RET 14, $noreg, implicit $r0 1097 ; CHECK: BX_RET 14, $noreg, implicit $r0 1098 ... 1099 --- 1100 name: test_mul_s32 1101 # CHECK-LABEL: name: test_mul_s32 1102 legalized: true 1103 regBankSelected: true 1104 selected: false 1105 # CHECK: selected: true 1106 registers: 1107 - { id: 0, class: gprb } 1108 - { id: 1, class: gprb } 1109 - { id: 2, class: gprb } 1110 body: | 1111 bb.0: 1112 liveins: $r0, $r1 1113 1114 %0(s32) = COPY $r0 1115 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 1116 1117 %1(s32) = COPY $r1 1118 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 1119 1120 %2(s32) = G_MUL %0, %1 1121 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, $noreg, $noreg 1122 1123 $r0 = COPY %2(s32) 1124 ; CHECK: $r0 = COPY [[VREGRES]] 1125 1126 BX_RET 14, $noreg, implicit $r0 1127 ; CHECK: BX_RET 14, $noreg, implicit $r0 1128 ... 1129 --- 1130 name: test_mulv5_s32 1131 # CHECK-LABEL: name: test_mulv5_s32 1132 legalized: true 1133 regBankSelected: true 1134 selected: false 1135 # CHECK: selected: true 1136 registers: 1137 - { id: 0, class: gprb } 1138 - { id: 1, class: gprb } 1139 - { id: 2, class: gprb } 1140 body: | 1141 bb.0: 1142 liveins: $r0, $r1 1143 1144 %0(s32) = COPY $r0 1145 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 1146 1147 %1(s32) = COPY $r1 1148 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 1149 1150 %2(s32) = G_MUL %0, %1 1151 ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg 1152 1153 $r0 = COPY %2(s32) 1154 ; CHECK: $r0 = COPY [[VREGRES]] 1155 1156 BX_RET 14, $noreg, implicit $r0 1157 ; CHECK: BX_RET 14, $noreg, implicit $r0 1158 ... 1159 --- 1160 name: test_sdiv_s32 1161 # CHECK-LABEL: name: test_sdiv_s32 1162 legalized: true 1163 regBankSelected: true 1164 selected: false 1165 # CHECK: selected: true 1166 registers: 1167 - { id: 0, class: gprb } 1168 - { id: 1, class: gprb } 1169 - { id: 2, class: gprb } 1170 body: | 1171 bb.0: 1172 liveins: $r0, $r1 1173 1174 %0(s32) = COPY $r0 1175 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1176 1177 %1(s32) = COPY $r1 1178 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1179 1180 %2(s32) = G_SDIV %0, %1 1181 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, $noreg 1182 1183 $r0 = COPY %2(s32) 1184 ; CHECK: $r0 = COPY [[VREGRES]] 1185 1186 BX_RET 14, $noreg, implicit $r0 1187 ; CHECK: BX_RET 14, $noreg, implicit $r0 1188 ... 1189 --- 1190 name: test_udiv_s32 1191 # CHECK-LABEL: name: test_udiv_s32 1192 legalized: true 1193 regBankSelected: true 1194 selected: false 1195 # CHECK: selected: true 1196 registers: 1197 - { id: 0, class: gprb } 1198 - { id: 1, class: gprb } 1199 - { id: 2, class: gprb } 1200 body: | 1201 bb.0: 1202 liveins: $r0, $r1 1203 1204 %0(s32) = COPY $r0 1205 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1206 1207 %1(s32) = COPY $r1 1208 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1209 1210 %2(s32) = G_UDIV %0, %1 1211 ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, $noreg 1212 1213 $r0 = COPY %2(s32) 1214 ; CHECK: $r0 = COPY [[VREGRES]] 1215 1216 BX_RET 14, $noreg, implicit $r0 1217 ; CHECK: BX_RET 14, $noreg, implicit $r0 1218 ... 1219 --- 1220 name: test_lshr_s32 1221 # CHECK-LABEL: name: test_lshr_s32 1222 legalized: true 1223 regBankSelected: true 1224 selected: false 1225 # CHECK: selected: true 1226 registers: 1227 - { id: 0, class: gprb } 1228 - { id: 1, class: gprb } 1229 - { id: 2, class: gprb } 1230 body: | 1231 bb.0: 1232 liveins: $r0, $r1 1233 1234 %0(s32) = COPY $r0 1235 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1236 1237 %1(s32) = COPY $r1 1238 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1239 1240 %2(s32) = G_LSHR %0, %1 1241 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, $noreg, $noreg 1242 1243 $r0 = COPY %2(s32) 1244 ; CHECK: $r0 = COPY [[VREGRES]] 1245 1246 BX_RET 14, $noreg, implicit $r0 1247 ; CHECK: BX_RET 14, $noreg, implicit $r0 1248 ... 1249 --- 1250 name: test_ashr_s32 1251 # CHECK-LABEL: name: test_ashr_s32 1252 legalized: true 1253 regBankSelected: true 1254 selected: false 1255 # CHECK: selected: true 1256 registers: 1257 - { id: 0, class: gprb } 1258 - { id: 1, class: gprb } 1259 - { id: 2, class: gprb } 1260 body: | 1261 bb.0: 1262 liveins: $r0, $r1 1263 1264 %0(s32) = COPY $r0 1265 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1266 1267 %1(s32) = COPY $r1 1268 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1269 1270 %2(s32) = G_ASHR %0, %1 1271 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, $noreg, $noreg 1272 1273 $r0 = COPY %2(s32) 1274 ; CHECK: $r0 = COPY [[VREGRES]] 1275 1276 BX_RET 14, $noreg, implicit $r0 1277 ; CHECK: BX_RET 14, $noreg, implicit $r0 1278 ... 1279 --- 1280 name: test_shl_s32 1281 # CHECK-LABEL: name: test_shl_s32 1282 legalized: true 1283 regBankSelected: true 1284 selected: false 1285 # CHECK: selected: true 1286 registers: 1287 - { id: 0, class: gprb } 1288 - { id: 1, class: gprb } 1289 - { id: 2, class: gprb } 1290 body: | 1291 bb.0: 1292 liveins: $r0, $r1 1293 1294 %0(s32) = COPY $r0 1295 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1296 1297 %1(s32) = COPY $r1 1298 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1299 1300 %2(s32) = G_SHL %0, %1 1301 ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, $noreg, $noreg 1302 1303 $r0 = COPY %2(s32) 1304 ; CHECK: $r0 = COPY [[VREGRES]] 1305 1306 BX_RET 14, $noreg, implicit $r0 1307 ; CHECK: BX_RET 14, $noreg, implicit $r0 1308 ... 1309 --- 1310 name: test_load_from_stack 1311 # CHECK-LABEL: name: test_load_from_stack 1312 legalized: true 1313 regBankSelected: true 1314 selected: false 1315 # CHECK: selected: true 1316 registers: 1317 - { id: 0, class: gprb } 1318 - { id: 1, class: gprb } 1319 - { id: 2, class: gprb } 1320 - { id: 3, class: gprb } 1321 - { id: 4, class: gprb } 1322 fixedStack: 1323 - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } 1324 - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } 1325 - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } 1326 # CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1 1327 # CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8 1328 body: | 1329 bb.0: 1330 liveins: $r0, $r1, $r2, $r3 1331 1332 %0(p0) = G_FRAME_INDEX %fixed-stack.2 1333 ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg 1334 1335 %1(s32) = G_LOAD %0(p0) :: (load 4) 1336 ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, $noreg 1337 1338 $r0 = COPY %1 1339 ; CHECK: $r0 = COPY [[LD32VREG]] 1340 1341 %2(p0) = G_FRAME_INDEX %fixed-stack.0 1342 ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg 1343 1344 %3(s1) = G_LOAD %2(p0) :: (load 1) 1345 ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, $noreg 1346 1347 %4(s32) = G_ANYEXT %3(s1) 1348 ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]] 1349 1350 $r0 = COPY %4 1351 ; CHECK: $r0 = COPY [[RES]] 1352 1353 BX_RET 14, $noreg 1354 ; CHECK: BX_RET 14, $noreg 1355 ... 1356 --- 1357 name: test_load_f32 1358 # CHECK-LABEL: name: test_load_f32 1359 legalized: true 1360 regBankSelected: true 1361 selected: false 1362 # CHECK: selected: true 1363 registers: 1364 - { id: 0, class: gprb } 1365 - { id: 1, class: fprb } 1366 body: | 1367 bb.0: 1368 liveins: $r0 1369 1370 %0(p0) = COPY $r0 1371 ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 1372 1373 %1(s32) = G_LOAD %0(p0) :: (load 4) 1374 ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, $noreg 1375 1376 $s0 = COPY %1 1377 ; CHECK: $s0 = COPY %[[V]] 1378 1379 BX_RET 14, $noreg, implicit $s0 1380 ; CHECK: BX_RET 14, $noreg, implicit $s0 1381 ... 1382 --- 1383 name: test_load_f64 1384 # CHECK-LABEL: name: test_load_f64 1385 legalized: true 1386 regBankSelected: true 1387 selected: false 1388 # CHECK: selected: true 1389 registers: 1390 - { id: 0, class: gprb } 1391 - { id: 1, class: fprb } 1392 body: | 1393 bb.0: 1394 liveins: $r0 1395 1396 %0(p0) = COPY $r0 1397 ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 1398 1399 %1(s64) = G_LOAD %0(p0) :: (load 8) 1400 ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, $noreg 1401 1402 $d0 = COPY %1 1403 ; CHECK: $d0 = COPY %[[V]] 1404 1405 BX_RET 14, $noreg, implicit $d0 1406 ; CHECK: BX_RET 14, $noreg, implicit $d0 1407 ... 1408 --- 1409 name: test_stores 1410 # CHECK-LABEL: name: test_stores 1411 legalized: true 1412 regBankSelected: true 1413 selected: false 1414 # CHECK: selected: true 1415 registers: 1416 - { id: 0, class: gprb } 1417 - { id: 1, class: gprb } 1418 - { id: 2, class: gprb } 1419 - { id: 3, class: gprb } 1420 - { id: 4, class: fprb } 1421 - { id: 5, class: fprb } 1422 # CHECK: id: [[P:[0-9]+]], class: gpr 1423 # CHECK: id: [[I8:[0-9]+]], class: gpr 1424 # CHECK: id: [[I16:[0-9]+]], class: gpr 1425 # CHECK: id: [[I32:[0-9]+]], class: gpr 1426 # CHECK: id: [[F32:[0-9]+]], class: spr 1427 # CHECK: id: [[F64:[0-9]+]], class: dpr 1428 body: | 1429 bb.0: 1430 liveins: $r0, $r1, $s0, $d0 1431 1432 %0(p0) = COPY $r0 1433 %3(s32) = COPY $r1 1434 %4(s32) = COPY $s0 1435 %5(s64) = COPY $d2 1436 %1(s8) = G_TRUNC %3(s32) 1437 %2(s16) = G_TRUNC %3(s32) 1438 1439 G_STORE %1(s8), %0(p0) :: (store 1) 1440 ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, $noreg 1441 1442 G_STORE %2(s16), %0(p0) :: (store 2) 1443 ; CHECK: STRH %[[I32]], %[[P]], $noreg, 0, 14, $noreg 1444 1445 G_STORE %3(s32), %0(p0) :: (store 4) 1446 ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, $noreg 1447 1448 G_STORE %4(s32), %0(p0) :: (store 4) 1449 ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, $noreg 1450 1451 G_STORE %5(s64), %0(p0) :: (store 8) 1452 ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, $noreg 1453 1454 BX_RET 14, $noreg 1455 ... 1456 --- 1457 name: test_gep 1458 # CHECK-LABEL: name: test_gep 1459 legalized: true 1460 regBankSelected: true 1461 selected: false 1462 # CHECK: selected: true 1463 registers: 1464 - { id: 0, class: gprb } 1465 - { id: 1, class: gprb } 1466 - { id: 2, class: gprb } 1467 body: | 1468 bb.0: 1469 liveins: $r0, $r1 1470 1471 %0(p0) = COPY $r0 1472 ; CHECK: %[[PTR:[0-9]+]]:gpr = COPY $r0 1473 1474 %1(s32) = COPY $r1 1475 ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY $r1 1476 1477 %2(p0) = G_GEP %0, %1(s32) 1478 ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, $noreg, $noreg 1479 1480 $r0 = COPY %2(p0) 1481 BX_RET 14, $noreg, implicit $r0 1482 ... 1483 --- 1484 name: test_constant_imm 1485 # CHECK-LABEL: name: test_constant_imm 1486 legalized: true 1487 regBankSelected: true 1488 selected: false 1489 # CHECK: selected: true 1490 registers: 1491 - { id: 0, class: gprb } 1492 body: | 1493 bb.0: 1494 %0(s32) = G_CONSTANT 42 1495 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg 1496 1497 $r0 = COPY %0(s32) 1498 BX_RET 14, $noreg, implicit $r0 1499 ... 1500 --- 1501 name: test_constant_cimm 1502 # CHECK-LABEL: name: test_constant_cimm 1503 legalized: true 1504 regBankSelected: true 1505 selected: false 1506 # CHECK: selected: true 1507 registers: 1508 - { id: 0, class: gprb } 1509 body: | 1510 bb.0: 1511 ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm. 1512 ; We still want to see the same thing in the output though. 1513 %0(s32) = G_CONSTANT i32 42 1514 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg 1515 1516 $r0 = COPY %0(s32) 1517 BX_RET 14, $noreg, implicit $r0 1518 ... 1519 --- 1520 name: test_pointer_constant_unconstrained 1521 # CHECK-LABEL: name: test_pointer_constant_unconstrained 1522 legalized: true 1523 regBankSelected: true 1524 selected: false 1525 # CHECK: selected: true 1526 registers: 1527 - { id: 0, class: gprb } 1528 body: | 1529 bb.0: 1530 %0(p0) = G_CONSTANT i32 0 1531 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg 1532 1533 ; This leaves %0 unconstrained before the G_CONSTANT is selected. 1534 $r0 = COPY %0(p0) 1535 BX_RET 14, $noreg, implicit $r0 1536 ... 1537 --- 1538 name: test_pointer_constant_constrained 1539 # CHECK-LABEL: name: test_pointer_constant_constrained 1540 legalized: true 1541 regBankSelected: true 1542 selected: false 1543 # CHECK: selected: true 1544 registers: 1545 - { id: 0, class: gprb } 1546 body: | 1547 bb.0: 1548 %0(p0) = G_CONSTANT i32 0 1549 ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg 1550 1551 ; This constrains %0 before the G_CONSTANT is selected. 1552 G_STORE %0(p0), %0(p0) :: (store 4) 1553 ... 1554 --- 1555 name: test_inttoptr_s32 1556 # CHECK-LABEL: name: test_inttoptr_s32 1557 legalized: true 1558 regBankSelected: true 1559 selected: false 1560 # CHECK: selected: true 1561 registers: 1562 - { id: 0, class: gprb } 1563 - { id: 1, class: gprb } 1564 body: | 1565 bb.0: 1566 liveins: $r0 1567 1568 %0(s32) = COPY $r0 1569 %1(p0) = G_INTTOPTR %0(s32) 1570 ; CHECK: [[INT:%[0-9]+]]:gpr = COPY $r0 1571 1572 $r0 = COPY %1(p0) 1573 ; CHECK: $r0 = COPY [[INT]] 1574 1575 BX_RET 14, $noreg, implicit $r0 1576 ... 1577 --- 1578 name: test_ptrtoint_s32 1579 # CHECK-LABEL: name: test_ptrtoint_s32 1580 legalized: true 1581 regBankSelected: true 1582 selected: false 1583 # CHECK: selected: true 1584 registers: 1585 - { id: 0, class: gprb } 1586 - { id: 1, class: gprb } 1587 body: | 1588 bb.0: 1589 liveins: $r0 1590 1591 %0(p0) = COPY $r0 1592 %1(s32) = G_PTRTOINT %0(p0) 1593 ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 1594 1595 $r0 = COPY %1(s32) 1596 ; CHECK: $r0 = COPY [[PTR]] 1597 1598 BX_RET 14, $noreg, implicit $r0 1599 ... 1600 --- 1601 name: test_select_s32 1602 # CHECK-LABEL: name: test_select_s32 1603 legalized: true 1604 regBankSelected: true 1605 selected: false 1606 # CHECK: selected: true 1607 registers: 1608 - { id: 0, class: gprb } 1609 - { id: 1, class: gprb } 1610 - { id: 2, class: gprb } 1611 - { id: 3, class: gprb } 1612 body: | 1613 bb.0: 1614 liveins: $r0, $r1 1615 1616 %0(s32) = COPY $r0 1617 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1618 1619 %1(s32) = COPY $r1 1620 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1621 1622 %2(s1) = G_TRUNC %1(s32) 1623 1624 %3(s32) = G_SELECT %2(s1), %0, %1 1625 ; CHECK: CMPri [[VREGY]], 0, 14, $noreg, implicit-def $cpsr 1626 ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr 1627 1628 $r0 = COPY %3(s32) 1629 ; CHECK: $r0 = COPY [[RES]] 1630 1631 BX_RET 14, $noreg, implicit $r0 1632 ; CHECK: BX_RET 14, $noreg, implicit $r0 1633 ... 1634 --- 1635 name: test_select_ptr 1636 # CHECK-LABEL: name: test_select_ptr 1637 legalized: true 1638 regBankSelected: true 1639 selected: false 1640 # CHECK: selected: true 1641 registers: 1642 - { id: 0, class: gprb } 1643 - { id: 1, class: gprb } 1644 - { id: 2, class: gprb } 1645 - { id: 3, class: gprb } 1646 - { id: 4, class: gprb } 1647 body: | 1648 bb.0: 1649 liveins: $r0, $r1, $r2 1650 1651 %0(p0) = COPY $r0 1652 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 1653 1654 %1(p0) = COPY $r1 1655 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 1656 1657 %2(s32) = COPY $r2 1658 ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY $r2 1659 1660 %3(s1) = G_TRUNC %2(s32) 1661 1662 %4(p0) = G_SELECT %3(s1), %0, %1 1663 ; CHECK: CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr 1664 ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr 1665 1666 $r0 = COPY %4(p0) 1667 ; CHECK: $r0 = COPY [[RES]] 1668 1669 BX_RET 14, $noreg, implicit $r0 1670 ; CHECK: BX_RET 14, $noreg, implicit $r0 1671 ... 1672 --- 1673 name: test_br 1674 # CHECK-LABEL: name: test_br 1675 legalized: true 1676 regBankSelected: true 1677 selected: false 1678 # CHECK: selected: true 1679 registers: 1680 - { id: 0, class: gprb } 1681 - { id: 1, class: gprb } 1682 body: | 1683 bb.0: 1684 ; CHECK: bb.0 1685 successors: %bb.1(0x40000000), %bb.2(0x40000000) 1686 liveins: $r0 1687 1688 %0(s32) = COPY $r0 1689 ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0 1690 %1(s1) = G_TRUNC %0(s32) 1691 1692 G_BRCOND %1(s1), %bb.1 1693 ; CHECK: TSTri [[COND32]], 1, 14, $noreg, implicit-def $cpsr 1694 ; CHECK: Bcc %bb.1, 1, $cpsr 1695 G_BR %bb.2 1696 ; CHECK: B %bb.2 1697 1698 bb.1: 1699 ; CHECK: bb.1 1700 successors: %bb.2(0x80000000) 1701 1702 G_BR %bb.2 1703 ; CHECK: B %bb.2 1704 1705 bb.2: 1706 ; CHECK: bb.2 1707 1708 BX_RET 14, $noreg 1709 ; CHECK: BX_RET 14, $noreg 1710 ... 1711 --- 1712 name: test_phi_s32 1713 # CHECK-LABEL: name: test_phi_s32 1714 legalized: true 1715 regBankSelected: true 1716 selected: false 1717 # CHECK: selected: true 1718 tracksRegLiveness: true 1719 registers: 1720 - { id: 0, class: gprb } 1721 - { id: 1, class: gprb } 1722 - { id: 2, class: gprb } 1723 - { id: 3, class: gprb } 1724 - { id: 4, class: gprb } 1725 body: | 1726 bb.0: 1727 ; CHECK: [[BB1:bb.0]]: 1728 successors: %bb.1(0x40000000), %bb.2(0x40000000) 1729 liveins: $r0, $r1, $r2 1730 1731 %0(s32) = COPY $r0 1732 %1(s1) = G_TRUNC %0(s32) 1733 1734 %2(s32) = COPY $r1 1735 %3(s32) = COPY $r2 1736 ; CHECK: [[V1:%[0-9]+]]:gpr = COPY $r1 1737 ; CHECK: [[V2:%[0-9]+]]:gpr = COPY $r2 1738 1739 G_BRCOND %1(s1), %bb.1 1740 G_BR %bb.2 1741 1742 bb.1: 1743 ; CHECK: [[BB2:bb.1]]: 1744 successors: %bb.2(0x80000000) 1745 1746 G_BR %bb.2 1747 ; CHECK: B %bb.2 1748 1749 bb.2: 1750 ; CHECK: bb.2 1751 %4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1 1752 ; CHECK: {{%[0-9]+}}:gpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]] 1753 1754 $r0 = COPY %4(s32) 1755 BX_RET 14, $noreg, implicit $r0 1756 ... 1757 --- 1758 name: test_phi_s64 1759 # CHECK-LABEL: name: test_phi_s64 1760 legalized: true 1761 regBankSelected: true 1762 selected: false 1763 # CHECK: selected: true 1764 tracksRegLiveness: true 1765 registers: 1766 - { id: 0, class: gprb } 1767 - { id: 1, class: gprb } 1768 - { id: 2, class: fprb } 1769 - { id: 3, class: fprb } 1770 - { id: 4, class: fprb } 1771 body: | 1772 bb.0: 1773 ; CHECK: [[BB1:bb.0]]: 1774 successors: %bb.1(0x40000000), %bb.2(0x40000000) 1775 liveins: $r0, $d0, $d1 1776 1777 %0(s32) = COPY $r0 1778 %1(s1) = G_TRUNC %0(s32) 1779 1780 %2(s64) = COPY $d0 1781 %3(s64) = COPY $d1 1782 ; CHECK: [[V1:%[0-9]+]]:dpr = COPY $d0 1783 ; CHECK: [[V2:%[0-9]+]]:dpr = COPY $d1 1784 1785 G_BRCOND %1(s1), %bb.1 1786 G_BR %bb.2 1787 1788 bb.1: 1789 ; CHECK: [[BB2:bb.1]]: 1790 successors: %bb.2(0x80000000) 1791 1792 G_BR %bb.2 1793 ; CHECK: B %bb.2 1794 1795 bb.2: 1796 ; CHECK: bb.2 1797 %4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1 1798 ; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]] 1799 1800 $d0 = COPY %4(s64) 1801 BX_RET 14, $noreg, implicit $d0 1802 ... 1803 --- 1804 name: test_soft_fp_double 1805 # CHECK-LABEL: name: test_soft_fp_double 1806 legalized: true 1807 regBankSelected: true 1808 selected: false 1809 # CHECK: selected: true 1810 registers: 1811 - { id: 0, class: gprb } 1812 - { id: 1, class: gprb } 1813 - { id: 2, class: fprb } 1814 - { id: 3, class: gprb } 1815 - { id: 4, class: gprb } 1816 body: | 1817 bb.0: 1818 liveins: $r0, $r1, $r2, $r3 1819 1820 %0(s32) = COPY $r2 1821 ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2 1822 1823 %1(s32) = COPY $r3 1824 ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3 1825 1826 %2(s64) = G_MERGE_VALUES %0(s32), %1(s32) 1827 ; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]] 1828 1829 %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64) 1830 ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]] 1831 1832 $r0 = COPY %3 1833 ; CHECK: $r0 = COPY [[OUT1]] 1834 1835 $r1 = COPY %4 1836 ; CHECK: $r1 = COPY [[OUT2]] 1837 1838 BX_RET 14, $noreg, implicit $r0, implicit $r1 1839 ; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 1840 ... 1841