1 ; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s 2 3 define i64 @f1(i64 %a, i64 %b) { 4 ; CHECK-LABEL: f1: 5 ; CHECK: subs r 6 ; CHECK: sbc r 7 entry: 8 %tmp = sub i64 %a, %b 9 ret i64 %tmp 10 } 11 12 define i64 @f2(i64 %a, i64 %b) { 13 ; CHECK-LABEL: f2: 14 ; CHECK: lsl r 15 ; CHECK: orr r 16 ; CHECK: rsbs r 17 ; CHECK: sbc r 18 entry: 19 %tmp1 = shl i64 %a, 1 20 %tmp2 = sub i64 %tmp1, %b 21 ret i64 %tmp2 22 } 23 24 ; add with live carry 25 define i64 @f3(i32 %al, i32 %bl) { 26 ; CHECK-LABEL: f3: 27 ; CHECK: adds r 28 ; CHECK: adc r 29 entry: 30 ; unsigned wide add 31 %aw = zext i32 %al to i64 32 %bw = zext i32 %bl to i64 33 %cw = add i64 %aw, %bw 34 ; ch == carry bit 35 %ch = lshr i64 %cw, 32 36 %dw = add i64 %ch, %bw 37 ret i64 %dw 38 } 39 40 ; rdar://10073745 41 define i64 @f4(i64 %x) nounwind readnone { 42 entry: 43 ; CHECK-LABEL: f4: 44 ; CHECK: rsbs r 45 ; CHECK: rsc r 46 %0 = sub nsw i64 0, %x 47 ret i64 %0 48 } 49 50 ; rdar://12559385 51 define i64 @f5(i32 %vi) { 52 entry: 53 ; CHECK-LABEL: f5: 54 ; CHECK: movw [[REG:r[0-9]+]], #36102 55 ; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]] 56 %v0 = zext i32 %vi to i64 57 %v1 = xor i64 %v0, -155057456198619 58 %v4 = add i64 %v1, 155057456198619 59 %v5 = add i64 %v4, %v1 60 ret i64 %v5 61 } 62
