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      1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
      2 ; RUN: llc < %s -mtriple thumbv7-eabi | FileCheck %s -check-prefix=T2
      3 ; RUN: llc < %s -mtriple thumbv6m-eabi | FileCheck %s -check-prefix=T1
      4 ; <rdar://problem/7569620>
      5 
      6 define i32 @compare_i_gt(i32 %a) {
      7 ; T2-LABEL: compare_i_gt:
      8 ; T2:       @ %bb.0: @ %entry
      9 ; T2-NEXT:    movs r1, #24
     10 ; T2-NEXT:    cmn.w r0, #78
     11 ; T2-NEXT:    it gt
     12 ; T2-NEXT:    movgt r1, #42
     13 ; T2-NEXT:    mov r0, r1
     14 ; T2-NEXT:    bx lr
     15 ;
     16 ; T1-LABEL: compare_i_gt:
     17 ; T1:       @ %bb.0: @ %entry
     18 ; T1-NEXT:    mov r1, r0
     19 ; T1-NEXT:    movs r0, #77
     20 ; T1-NEXT:    mvns r3, r0
     21 ; T1-NEXT:    movs r0, #42
     22 ; T1-NEXT:    movs r2, #24
     23 ; T1-NEXT:    cmp r1, r3
     24 ; T1-NEXT:    bgt .LBB0_2
     25 ; T1-NEXT:  @ %bb.1: @ %entry
     26 ; T1-NEXT:    mov r0, r2
     27 ; T1-NEXT:  .LBB0_2: @ %entry
     28 ; T1-NEXT:    bx lr
     29 entry:
     30   %cmp = icmp sgt i32 %a, -78
     31   %ret = select i1 %cmp, i32 42, i32 24
     32   ret i32 %ret
     33 }
     34 
     35 define i32 @compare_r_eq(i32 %a, i32 %b) {
     36 ; T2-LABEL: compare_r_eq:
     37 ; T2:       @ %bb.0: @ %entry
     38 ; T2-NEXT:    movs r2, #24
     39 ; T2-NEXT:    cmn r0, r1
     40 ; T2-NEXT:    it eq
     41 ; T2-NEXT:    moveq r2, #42
     42 ; T2-NEXT:    mov r0, r2
     43 ; T2-NEXT:    bx lr
     44 ;
     45 ; T1-LABEL: compare_r_eq:
     46 ; T1:       @ %bb.0: @ %entry
     47 ; T1-NEXT:    mov r2, r0
     48 ; T1-NEXT:    movs r0, #42
     49 ; T1-NEXT:    movs r3, #24
     50 ; T1-NEXT:    cmn r2, r1
     51 ; T1-NEXT:    beq .LBB1_2
     52 ; T1-NEXT:  @ %bb.1: @ %entry
     53 ; T1-NEXT:    mov r0, r3
     54 ; T1-NEXT:  .LBB1_2: @ %entry
     55 ; T1-NEXT:    bx lr
     56 entry:
     57   %sub = sub nsw i32 0, %b
     58   %cmp = icmp eq i32 %a, %sub
     59   %ret = select i1 %cmp, i32 42, i32 24
     60   ret i32 %ret
     61 }
     62