1 ; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s 2 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-T2 3 4 define i1 @f1(i32 %a, i32 %b) { 5 ; CHECK-LABEL: f1: 6 ; CHECK: subs r0, r0, r1 7 ; CHECK: movwne r0, #1 8 ; CHECK-T2: subs r0, r0, r1 9 ; CHECK-T2: it ne 10 ; CHECK-T2: movne r0, #1 11 %tmp = icmp ne i32 %a, %b 12 ret i1 %tmp 13 } 14 15 define i1 @f2(i32 %a, i32 %b) { 16 ; CHECK-LABEL: f2: 17 ; CHECK: sub r0, r0, r1 18 ; CHECK: clz r0, r0 19 ; CHECK: lsr r0, r0, #5 20 ; CHECK-T2: subs r0, r0, r1 21 ; CHECK-T2: clz r0, r0 22 ; CHECK-T2: lsrs r0, r0, #5 23 %tmp = icmp eq i32 %a, %b 24 ret i1 %tmp 25 } 26 27 define i1 @f6(i32 %a, i32 %b) { 28 ; CHECK-LABEL: f6: 29 ; CHECK: sub r0, r0, r1, lsl #5 30 ; CHECK: clz r0, r0 31 ; CHECK: lsr r0, r0, #5 32 ; CHECK-T2: sub.w r0, r0, r1, lsl #5 33 ; CHECK-T2: clz r0, r0 34 ; CHECK-T2: lsrs r0, r0, #5 35 %tmp = shl i32 %b, 5 36 %tmp1 = icmp eq i32 %a, %tmp 37 ret i1 %tmp1 38 } 39 40 define i1 @f7(i32 %a, i32 %b) { 41 ; CHECK-LABEL: f7: 42 ; CHECK: sub r2, r0, r1, lsr #6 43 ; CHECK: cmp r0, r1, lsr #6 44 ; CHECK: movwne r2, #1 45 ; CHECK: mov r0, r2 46 ; CHECK-T2: sub.w r2, r0, r1, lsr #6 47 ; CHECK-T2: cmp.w r0, r1, lsr #6 48 ; CHECK-T2: it ne 49 ; CHECK-T2: movne r2, #1 50 ; CHECK-T2: mov r0, r2 51 %tmp = lshr i32 %b, 6 52 %tmp1 = icmp ne i32 %a, %tmp 53 ret i1 %tmp1 54 } 55 56 define i1 @f8(i32 %a, i32 %b) { 57 ; CHECK-LABEL: f8: 58 ; CHECK: sub r0, r0, r1, asr #7 59 ; CHECK: clz r0, r0 60 ; CHECK: lsr r0, r0, #5 61 ; CHECK-T2: sub.w r0, r0, r1, asr #7 62 ; CHECK-T2: clz r0, r0 63 ; CHECK-T2: lsrs r0, r0, #5 64 %tmp = ashr i32 %b, 7 65 %tmp1 = icmp eq i32 %a, %tmp 66 ret i1 %tmp1 67 } 68 69 define i1 @f9(i32 %a) { 70 ; CHECK-LABEL: f9: 71 ; CHECK: sub r1, r0, r0, ror #8 72 ; CHECK: cmp r0, r0, ror #8 73 ; CHECK: movwne r1, #1 74 ; CHECK: mov r0, r1 75 ; CHECK-T2: sub.w r1, r0, r0, ror #8 76 ; CHECK-T2: cmp.w r0, r0, ror #8 77 ; CHECK-T2: it ne 78 ; CHECK-T2: movne r1, #1 79 ; CHECK-T2: mov r0, r1 80 %l8 = shl i32 %a, 24 81 %r8 = lshr i32 %a, 8 82 %tmp = or i32 %l8, %r8 83 %tmp1 = icmp ne i32 %a, %tmp 84 ret i1 %tmp1 85 } 86 87 ; CHECK-LABEL: swap_cmp_shl 88 ; CHECK: mov r2, #0 89 ; CHECK: cmp r1, r0, lsl #11 90 ; CHECK: movwlt r2, #1 91 ; CHECK-T2: mov{{.*}} r2, #0 92 ; CHECK-T2: cmp.w r1, r0, lsl #11 93 ; CHECK-T2: movlt r2, #1 94 define arm_aapcscc i32 @swap_cmp_shl(i32 %a, i32 %b) { 95 entry: 96 %shift = shl i32 %a, 11 97 %cmp = icmp sgt i32 %shift, %b 98 %conv = zext i1 %cmp to i32 99 ret i32 %conv 100 } 101 102 ; CHECK-LABEL: swap_cmp_lshr 103 ; CHECK: mov r2, #0 104 ; CHECK: cmp r1, r0, lsr #11 105 ; CHECK: movwhi r2, #1 106 ; CHECK-T2: mov{{.*}} r2, #0 107 ; CHECK-T2: cmp.w r1, r0, lsr #11 108 ; CHECK-T2: movhi r2, #1 109 define arm_aapcscc i32 @swap_cmp_lshr(i32 %a, i32 %b) { 110 entry: 111 %shift = lshr i32 %a, 11 112 %cmp = icmp ult i32 %shift, %b 113 %conv = zext i1 %cmp to i32 114 ret i32 %conv 115 } 116 117 ; CHECK-LABEL: swap_cmp_ashr 118 ; CHECK: mov r2, #0 119 ; CHECK: cmp r1, r0, asr #11 120 ; CHECK: movwle r2, #1 121 ; CHECK-T2: mov{{.*}} r2, #0 122 ; CHECK-T2: cmp.w r1, r0, asr #11 123 ; CHECK-T2: movle r2, #1 124 define arm_aapcscc i32 @swap_cmp_ashr(i32 %a, i32 %b) { 125 entry: 126 %shift = ashr i32 %a, 11 127 %cmp = icmp sge i32 %shift, %b 128 %conv = zext i1 %cmp to i32 129 ret i32 %conv 130 } 131 132 ; CHECK-LABEL: swap_cmp_rotr 133 ; CHECK: mov r2, #0 134 ; CHECK: cmp r1, r0, ror #11 135 ; CHECK: movwls r2, #1 136 ; CHECK-T2: mov{{.*}} r2, #0 137 ; CHECK-T2: cmp.w r1, r0, ror #11 138 ; CHECK-T2: movls r2, #1 139 define arm_aapcscc i32 @swap_cmp_rotr(i32 %a, i32 %b) { 140 entry: 141 %lsr = lshr i32 %a, 11 142 %lsl = shl i32 %a, 21 143 %ror = or i32 %lsr, %lsl 144 %cmp = icmp uge i32 %ror, %b 145 %conv = zext i1 %cmp to i32 146 ret i32 %conv 147 } 148
