1 # RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s 2 3 # Here we check that the peephole cmp rewrite is not triggered, because 4 # there is store instruction between the tMUL and tCMP, i.e. there are 5 # no constants to reorder. 6 7 --- | 8 ; ModuleID = 'cmp2-peephole-thumb.ll' 9 source_filename = "<stdin>" 10 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 11 target triple = "thumb-none--eabi" 12 13 define i32 @g(i32 %a, i32 %b) { 14 entry: 15 %retval = alloca i32, align 4 16 %mul = alloca i32, align 4 17 %mul1 = mul nsw i32 %a, %b 18 store i32 %mul1, i32* %mul, align 4 19 %0 = load i32, i32* %mul, align 4 20 %cmp = icmp sle i32 %0, 0 21 br i1 %cmp, label %if.then, label %if.end 22 23 if.then: ; preds = %entry 24 store i32 42, i32* %retval, align 4 25 br label %return 26 27 if.end: ; preds = %entry 28 store i32 1, i32* %retval, align 4 29 br label %return 30 31 return: ; preds = %if.end, %if.then 32 %1 = load i32, i32* %retval, align 4 33 ret i32 %1 34 } 35 36 ... 37 --- 38 name: g 39 # CHECK-LABEL: name: g 40 alignment: 1 41 exposesReturnsTwice: false 42 legalized: false 43 regBankSelected: false 44 selected: false 45 tracksRegLiveness: true 46 registers: 47 - { id: 0, class: tgpr } 48 - { id: 1, class: tgpr } 49 - { id: 2, class: tgpr } 50 - { id: 3, class: tgpr } 51 - { id: 4, class: tgpr } 52 - { id: 5, class: tgpr } 53 liveins: 54 - { reg: '$r0', virtual-reg: '%0' } 55 - { reg: '$r1', virtual-reg: '%1' } 56 frameInfo: 57 isFrameAddressTaken: false 58 isReturnAddressTaken: false 59 hasStackMap: false 60 hasPatchPoint: false 61 stackSize: 0 62 offsetAdjustment: 0 63 maxAlignment: 4 64 adjustsStack: false 65 hasCalls: false 66 maxCallFrameSize: 0 67 hasOpaqueSPAdjustment: false 68 hasVAStart: false 69 hasMustTailInVarArgFunc: false 70 stack: 71 - { id: 0, name: retval, offset: 0, size: 4, alignment: 4, local-offset: -4 } 72 - { id: 1, name: mul, offset: 0, size: 4, alignment: 4, local-offset: -8 } 73 74 # CHECK: tMUL 75 # CHECK-NEXT: tSTRspi 76 # CHECK-NEXT: tCMPi8 77 body: | 78 bb.0.entry: 79 liveins: $r0, $r1 80 81 %1 = COPY $r1 82 %0 = COPY $r0 83 %2, $cpsr = tMUL %0, %1, 14, $noreg 84 tSTRspi %2, %stack.1.mul, 0, 14, $noreg :: (store 4 into %ir.mul) 85 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr 86 tBcc %bb.2.if.end, 12, $cpsr 87 tB %bb.1.if.then, 14, $noreg 88 89 bb.1.if.then: 90 %4, $cpsr = tMOVi8 42, 14, $noreg 91 tSTRspi killed %4, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval) 92 tB %bb.3.return, 14, $noreg 93 94 bb.2.if.end: 95 %3, $cpsr = tMOVi8 1, 14, $noreg 96 tSTRspi killed %3, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval) 97 98 bb.3.return: 99 %5 = tLDRspi %stack.0.retval, 0, 14, $noreg :: (dereferenceable load 4 from %ir.retval) 100 $r0 = COPY %5 101 tBX_RET 14, $noreg, implicit $r0 102 103 ... 104
