1 ; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s 2 ; 3 ; The Cortex-M0 does not support unaligned accesses: 4 ; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED 5 ; 6 ; Check DSP extension: 7 ; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED 8 9 define dso_local i32 @OneReduction(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { 10 ; 11 ; CHECK-LABEL: @OneReduction 12 ; CHECK: %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ] 13 ; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32* 14 ; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]], align 2 15 ; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx to i32* 16 ; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]], align 2 17 ; CHECK: [[V8]] = call i32 @llvm.arm.smlad(i32 [[V5]], i32 [[V7]], i32 %mac1{{\.}}026) 18 ; CHECK-NOT: call i32 @llvm.arm.smlad 19 ; 20 ; CHECK-UNSUPPORTED-NOT: call i32 @llvm.arm.smlad 21 ; 22 entry: 23 %cmp24 = icmp sgt i32 %arg, 0 24 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup 25 26 for.body.preheader: 27 %.pre = load i16, i16* %arg3, align 2 28 %.pre27 = load i16, i16* %arg2, align 2 29 br label %for.body 30 31 for.cond.cleanup: 32 %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ] 33 ret i32 %mac1.0.lcssa 34 35 for.body: 36 ; One reduction statement here: 37 %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ] 38 39 %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] 40 %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025 41 %0 = load i16, i16* %arrayidx, align 2 42 %add = add nuw nsw i32 %i.025, 1 43 %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add 44 %1 = load i16, i16* %arrayidx1, align 2 45 %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025 46 %2 = load i16, i16* %arrayidx3, align 2 47 %conv = sext i16 %2 to i32 48 %conv4 = sext i16 %0 to i32 49 %mul = mul nsw i32 %conv, %conv4 50 %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add 51 %3 = load i16, i16* %arrayidx6, align 2 52 %conv7 = sext i16 %3 to i32 53 %conv8 = sext i16 %1 to i32 54 %mul9 = mul nsw i32 %conv7, %conv8 55 %add10 = add i32 %mul, %mac1.026 56 57 ; Here the Mul is the LHS, and the Add the RHS. 58 %add11 = add i32 %mul9, %add10 59 60 %exitcond = icmp ne i32 %add, %arg 61 br i1 %exitcond, label %for.body, label %for.cond.cleanup 62 } 63 64 define dso_local arm_aapcs_vfpcc i32 @TwoReductions(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { 65 ; 66 ; CHECK-LABEL: @TwoReductions 67 ; 68 ; CHECK: %mac1{{\.}}058 = phi i32 [ [[V10:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ] 69 ; CHECK: %mac2{{\.}}057 = phi i32 [ [[V17:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ] 70 ; CHECK: [[V10]] = call i32 @llvm.arm.smlad(i32 %{{.*}}, i32 %{{.*}}, i32 %mac1{{\.}}058) 71 ; CHECK: [[V17]] = call i32 @llvm.arm.smlad(i32 %{{.*}}, i32 %{{.*}}, i32 %mac2{{\.}}057) 72 ; CHECK-NOT: call i32 @llvm.arm.smlad 73 ; 74 entry: 75 %cmp55 = icmp sgt i32 %arg, 0 76 br i1 %cmp55, label %for.body.preheader, label %for.cond.cleanup 77 78 for.cond.cleanup: 79 %mac2.0.lcssa = phi i32 [ 0, %entry ], [ %add28, %for.body ] 80 %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add16, %for.body ] 81 %add30 = add nsw i32 %mac1.0.lcssa, %mac2.0.lcssa 82 ret i32 %add30 83 84 for.body.preheader: 85 br label %for.body 86 87 for.body: 88 ; And two reduction statements here: 89 %mac1.058 = phi i32 [ %add16, %for.body ], [ 0, %for.body.preheader ] 90 %mac2.057 = phi i32 [ %add28, %for.body ], [ 0, %for.body.preheader ] 91 92 %i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ] 93 %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.056 94 %0 = load i16, i16* %arrayidx, align 2 95 %add1 = or i32 %i.056, 1 96 %arrayidx2 = getelementptr inbounds i16, i16* %arg3, i32 %add1 97 %1 = load i16, i16* %arrayidx2, align 2 98 %add3 = or i32 %i.056, 2 99 %arrayidx4 = getelementptr inbounds i16, i16* %arg3, i32 %add3 100 %2 = load i16, i16* %arrayidx4, align 2 101 102 %add5 = or i32 %i.056, 3 103 %arrayidx6 = getelementptr inbounds i16, i16* %arg3, i32 %add5 104 %3 = load i16, i16* %arrayidx6, align 2 105 %arrayidx8 = getelementptr inbounds i16, i16* %arg2, i32 %i.056 106 %4 = load i16, i16* %arrayidx8, align 2 107 %conv = sext i16 %4 to i32 108 %conv9 = sext i16 %0 to i32 109 %mul = mul nsw i32 %conv, %conv9 110 %arrayidx11 = getelementptr inbounds i16, i16* %arg2, i32 %add1 111 %5 = load i16, i16* %arrayidx11, align 2 112 %conv12 = sext i16 %5 to i32 113 %conv13 = sext i16 %1 to i32 114 %mul14 = mul nsw i32 %conv12, %conv13 115 %add15 = add i32 %mul, %mac1.058 116 %add16 = add i32 %add15, %mul14 117 %arrayidx18 = getelementptr inbounds i16, i16* %arg2, i32 %add3 118 %6 = load i16, i16* %arrayidx18, align 2 119 %conv19 = sext i16 %6 to i32 120 %conv20 = sext i16 %2 to i32 121 %mul21 = mul nsw i32 %conv19, %conv20 122 %arrayidx23 = getelementptr inbounds i16, i16* %arg2, i32 %add5 123 %7 = load i16, i16* %arrayidx23, align 2 124 %conv24 = sext i16 %7 to i32 125 %conv25 = sext i16 %3 to i32 126 %mul26 = mul nsw i32 %conv24, %conv25 127 %add27 = add i32 %mul21, %mac2.057 128 %add28 = add i32 %add27, %mul26 129 %add29 = add nuw nsw i32 %i.056, 4 130 %cmp = icmp slt i32 %add29, %arg 131 br i1 %cmp, label %for.body, label %for.cond.cleanup 132 } 133
