1 ; REQUIRES: asserts 2 ; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 --stats -o - 2>&1 < %s | FileCheck %s 3 ; This was aborting while processing SUnits. 4 5 ; CHECK: vmem 6 7 ; CHECK-NOT: Number of node order issues found 8 ; CHECK: Number of loops software pipelined 9 ; CHECK-NOT: Number of node order issues found 10 source_filename = "bugpoint-output-bdb0052.bc" 11 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 12 target triple = "hexagon-unknown--elf" 13 14 ; Function Attrs: nounwind readnone 15 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0 16 17 ; Function Attrs: nounwind readnone 18 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0 19 20 ; Function Attrs: nounwind readnone 21 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #0 22 23 ; Function Attrs: nounwind readnone 24 declare <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32>, <16 x i32>, i32) #0 25 26 ; Function Attrs: nounwind readnone 27 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0 28 29 ; Function Attrs: nounwind readnone 30 declare <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32>, <16 x i32>) #0 31 32 ; Function Attrs: nounwind readnone 33 declare <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32>, <16 x i32>) #0 34 35 ; Function Attrs: nounwind readnone 36 declare <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32>, <16 x i32>) #0 37 38 ; Function Attrs: nounwind readnone 39 declare <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32>, <16 x i32>, i32) #0 40 41 define void @__error_op_vmpy_v__uh_v__uh__1() #1 { 42 entry: 43 %in_u16.host181 = load i16*, i16** undef, align 4 44 %in_u32.host182 = load i32*, i32** undef, align 4 45 br label %"for op_vmpy_v__uh_v__uh__1.s0.y" 46 47 "for op_vmpy_v__uh_v__uh__1.s0.y": ; preds = %"end for op_vmpy_v__uh_v__uh__1.s0.x.x", %entry 48 %op_vmpy_v__uh_v__uh__1.s0.y = phi i32 [ 0, %entry ], [ %63, %"end for op_vmpy_v__uh_v__uh__1.s0.x.x" ] 49 %0 = mul nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.y, 768 50 %1 = add nuw nsw i32 %0, 32 51 %2 = add nuw nsw i32 %0, 64 52 %3 = add nuw nsw i32 %0, 96 53 br label %"for op_vmpy_v__uh_v__uh__1.s0.x.x" 54 55 "for op_vmpy_v__uh_v__uh__1.s0.x.x": ; preds = %"for op_vmpy_v__uh_v__uh__1.s0.x.x", %"for op_vmpy_v__uh_v__uh__1.s0.y" 56 %.phi210 = phi i32* [ %in_u32.host182, %"for op_vmpy_v__uh_v__uh__1.s0.y" ], [ %.inc211.3, %"for op_vmpy_v__uh_v__uh__1.s0.x.x" ] 57 %.phi213 = phi i16* [ %in_u16.host181, %"for op_vmpy_v__uh_v__uh__1.s0.y" ], [ %.inc214.3, %"for op_vmpy_v__uh_v__uh__1.s0.x.x" ] 58 %op_vmpy_v__uh_v__uh__1.s0.x.x = phi i32 [ 0, %"for op_vmpy_v__uh_v__uh__1.s0.y" ], [ %61, %"for op_vmpy_v__uh_v__uh__1.s0.x.x" ] 59 %4 = mul nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.x.x, 32 60 %5 = bitcast i32* %.phi210 to <16 x i32>* 61 %6 = load <16 x i32>, <16 x i32>* %5, align 64, !tbaa !1 62 %7 = add nuw nsw i32 %4, 16 63 %8 = getelementptr inbounds i32, i32* %in_u32.host182, i32 %7 64 %9 = bitcast i32* %8 to <16 x i32>* 65 %10 = load <16 x i32>, <16 x i32>* %9, align 64, !tbaa !1 66 %11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %10, <16 x i32> %6) 67 %e.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %11) #2 68 %o.i = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %11) #2 69 %r.i = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %o.i, <16 x i32> %e.i, i32 -4) #2 70 %12 = bitcast i16* %.phi213 to <16 x i32>* 71 %13 = load <16 x i32>, <16 x i32>* %12, align 64, !tbaa !4 72 %a_lo.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i) #2 73 %a_hi.i = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i) #2 74 %a_e.i = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %a_hi.i, <16 x i32> %a_lo.i) #2 75 %a_o.i = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %a_hi.i, <16 x i32> %a_lo.i) #2 76 %ab_e.i = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_e.i, <16 x i32> %13) #2 77 %ab_o.i = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_o.i, <16 x i32> %13) #2 78 %a_lo.i.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_e.i) #2 79 %l_lo.i.i = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_o.i) #2 80 %s_lo.i.i = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_lo.i.i, <16 x i32> %l_lo.i.i, i32 16) #2 81 %l_hi.i.i = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_o.i) #2 82 %s_hi.i.i = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> undef, <16 x i32> %l_hi.i.i, i32 16) #2 83 %s.i.i = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %s_hi.i.i, <16 x i32> %s_lo.i.i) #2 84 %e.i189 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %s.i.i) #2 85 %o.i190 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %s.i.i) #2 86 %r.i191 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %o.i190, <16 x i32> %e.i189, i32 -4) #2 87 %14 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191) 88 %15 = add nuw nsw i32 %4, %0 89 %16 = getelementptr inbounds i32, i32* undef, i32 %15 90 %17 = bitcast i32* %16 to <16 x i32>* 91 store <16 x i32> %14, <16 x i32>* %17, align 64, !tbaa !6 92 %18 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191) 93 store <16 x i32> %18, <16 x i32>* undef, align 64, !tbaa !6 94 %.inc211 = getelementptr i32, i32* %.phi210, i32 32 95 %.inc214 = getelementptr i16, i16* %.phi213, i32 32 96 %19 = bitcast i32* %.inc211 to <16 x i32>* 97 %20 = load <16 x i32>, <16 x i32>* %19, align 64, !tbaa !1 98 %21 = add nuw nsw i32 %4, 48 99 %22 = getelementptr inbounds i32, i32* %in_u32.host182, i32 %21 100 %23 = bitcast i32* %22 to <16 x i32>* 101 %24 = load <16 x i32>, <16 x i32>* %23, align 64, !tbaa !1 102 %25 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %24, <16 x i32> %20) 103 %e.i.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %25) #2 104 %r.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> undef, <16 x i32> %e.i.1, i32 -4) #2 105 %26 = bitcast i16* %.inc214 to <16 x i32>* 106 %27 = load <16 x i32>, <16 x i32>* %26, align 64, !tbaa !4 107 %a_lo.i.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i.1) #2 108 %a_e.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> undef, <16 x i32> %a_lo.i.1) #2 109 %a_o.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> undef, <16 x i32> %a_lo.i.1) #2 110 %ab_e.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_e.i.1, <16 x i32> %27) #2 111 %ab_o.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_o.i.1, <16 x i32> %27) #2 112 %a_lo.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_e.i.1) #2 113 %s_lo.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_lo.i.i.1, <16 x i32> undef, i32 16) #2 114 %a_hi.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_e.i.1) #2 115 %l_hi.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_o.i.1) #2 116 %s_hi.i.i.1 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_hi.i.i.1, <16 x i32> %l_hi.i.i.1, i32 16) #2 117 %s.i.i.1 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %s_hi.i.i.1, <16 x i32> %s_lo.i.i.1) #2 118 %e.i189.1 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %s.i.i.1) #2 119 %o.i190.1 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %s.i.i.1) #2 120 %r.i191.1 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %o.i190.1, <16 x i32> %e.i189.1, i32 -4) #2 121 %28 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191.1) 122 %29 = add nuw nsw i32 %1, %4 123 %30 = getelementptr inbounds i32, i32* undef, i32 %29 124 %31 = bitcast i32* %30 to <16 x i32>* 125 store <16 x i32> %28, <16 x i32>* %31, align 64, !tbaa !6 126 %32 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191.1) 127 %33 = add nuw nsw i32 %29, 16 128 %34 = getelementptr inbounds i32, i32* undef, i32 %33 129 %35 = bitcast i32* %34 to <16 x i32>* 130 store <16 x i32> %32, <16 x i32>* %35, align 64, !tbaa !6 131 %.inc211.1 = getelementptr i32, i32* %.phi210, i32 64 132 %.inc214.1 = getelementptr i16, i16* %.phi213, i32 64 133 %36 = bitcast i32* %.inc211.1 to <16 x i32>* 134 %37 = load <16 x i32>, <16 x i32>* %36, align 64, !tbaa !1 135 %38 = add nuw nsw i32 %4, 80 136 %39 = getelementptr inbounds i32, i32* %in_u32.host182, i32 %38 137 %40 = bitcast i32* %39 to <16 x i32>* 138 %41 = load <16 x i32>, <16 x i32>* %40, align 64, !tbaa !1 139 %42 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %41, <16 x i32> %37) 140 %e.i.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %42) #2 141 %o.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %42) #2 142 %r.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %o.i.2, <16 x i32> %e.i.2, i32 -4) #2 143 %43 = bitcast i16* %.inc214.1 to <16 x i32>* 144 %44 = load <16 x i32>, <16 x i32>* %43, align 64, !tbaa !4 145 %a_lo.i.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i.2) #2 146 %a_hi.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i.2) #2 147 %a_e.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %a_hi.i.2, <16 x i32> %a_lo.i.2) #2 148 %a_o.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %a_hi.i.2, <16 x i32> %a_lo.i.2) #2 149 %ab_e.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_e.i.2, <16 x i32> %44) #2 150 %ab_o.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %a_o.i.2, <16 x i32> %44) #2 151 %l_lo.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %ab_o.i.2) #2 152 %s_lo.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> undef, <16 x i32> %l_lo.i.i.2, i32 16) #2 153 %a_hi.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_e.i.2) #2 154 %l_hi.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %ab_o.i.2) #2 155 %s_hi.i.i.2 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %a_hi.i.i.2, <16 x i32> %l_hi.i.i.2, i32 16) #2 156 %s.i.i.2 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %s_hi.i.i.2, <16 x i32> %s_lo.i.i.2) #2 157 %e.i189.2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %s.i.i.2) #2 158 %o.i190.2 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %s.i.i.2) #2 159 %r.i191.2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %o.i190.2, <16 x i32> %e.i189.2, i32 -4) #2 160 %45 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191.2) 161 %46 = add nuw nsw i32 %2, %4 162 %47 = getelementptr inbounds i32, i32* undef, i32 %46 163 %48 = bitcast i32* %47 to <16 x i32>* 164 store <16 x i32> %45, <16 x i32>* %48, align 64, !tbaa !6 165 %49 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191.2) 166 %50 = add nuw nsw i32 %46, 16 167 %51 = getelementptr inbounds i32, i32* undef, i32 %50 168 %52 = bitcast i32* %51 to <16 x i32>* 169 store <16 x i32> %49, <16 x i32>* %52, align 64, !tbaa !6 170 %e.i189.3 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> undef) #2 171 %r.i191.3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %e.i189.3, i32 -4) #2 172 %53 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %r.i191.3) 173 %54 = add nuw nsw i32 %3, %4 174 %55 = getelementptr inbounds i32, i32* undef, i32 %54 175 %56 = bitcast i32* %55 to <16 x i32>* 176 store <16 x i32> %53, <16 x i32>* %56, align 64, !tbaa !6 177 %57 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %r.i191.3) 178 %58 = add nuw nsw i32 %54, 16 179 %59 = getelementptr inbounds i32, i32* undef, i32 %58 180 %60 = bitcast i32* %59 to <16 x i32>* 181 store <16 x i32> %57, <16 x i32>* %60, align 64, !tbaa !6 182 %61 = add nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.x.x, 4 183 %62 = icmp eq i32 %61, 24 184 %.inc211.3 = getelementptr i32, i32* %.phi210, i32 128 185 %.inc214.3 = getelementptr i16, i16* %.phi213, i32 128 186 br i1 %62, label %"end for op_vmpy_v__uh_v__uh__1.s0.x.x", label %"for op_vmpy_v__uh_v__uh__1.s0.x.x" 187 188 "end for op_vmpy_v__uh_v__uh__1.s0.x.x": ; preds = %"for op_vmpy_v__uh_v__uh__1.s0.x.x" 189 %63 = add nuw nsw i32 %op_vmpy_v__uh_v__uh__1.s0.y, 1 190 br label %"for op_vmpy_v__uh_v__uh__1.s0.y" 191 } 192 193 attributes #0 = { nounwind readnone } 194 attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 195 attributes #2 = { nounwind } 196 197 !llvm.module.flags = !{!0} 198 199 !0 = !{i32 2, !"halide_mattrs", !"+hvx"} 200 !1 = !{!2, !2, i64 0} 201 !2 = !{!"in_u32", !3} 202 !3 = !{!"Halide buffer"} 203 !4 = !{!5, !5, i64 0} 204 !5 = !{!"in_u16", !3} 205 !6 = !{!7, !7, i64 0} 206 !7 = !{!"op_vmpy_v__uh_v__uh__1", !3} 207
