1 ; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s 2 ; Check that we generate load instructions with absolute addressing mode. 3 4 @a0 = external global i32 5 @a1 = external global i32 6 @b0 = external global i8 7 @b1 = external global i8 8 @c0 = external global i16 9 @c1 = external global i16 10 @d = external global i64 11 12 define zeroext i8 @absStoreByte() nounwind { 13 ; CHECK: memb(##b1) = r{{[0-9]+}} 14 entry: 15 %0 = load i8, i8* @b0, align 1 16 %conv = zext i8 %0 to i32 17 %mul = mul nsw i32 100, %conv 18 %conv1 = trunc i32 %mul to i8 19 store i8 %conv1, i8* @b1, align 1 20 ret i8 %conv1 21 } 22 23 define signext i16 @absStoreHalf() nounwind { 24 ; CHECK: memh(##c1) = r{{[0-9]+}} 25 entry: 26 %0 = load i16, i16* @c0, align 2 27 %conv = sext i16 %0 to i32 28 %mul = mul nsw i32 100, %conv 29 %conv1 = trunc i32 %mul to i16 30 store i16 %conv1, i16* @c1, align 2 31 ret i16 %conv1 32 } 33 34 define i32 @absStoreWord() nounwind { 35 ; CHECK: memw(##a1) = r{{[0-9]+}} 36 entry: 37 %0 = load i32, i32* @a0, align 4 38 %mul = mul nsw i32 100, %0 39 store i32 %mul, i32* @a1, align 4 40 ret i32 %mul 41 } 42 43 define void @absStoreDouble() nounwind { 44 ; CHECK: memd(##d) = r{{[0-9]+}}:{{[0-9]+}} 45 entry: 46 store i64 100, i64* @d, align 8 47 ret void 48 } 49 50
