1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; 3 ; Check if we generate rounding-asr instruction. It is equivalent to 4 ; Rd = ((Rs >> #u) +1) >> 1. 5 6 target triple = "hexagon" 7 8 define i32 @f0(i32 %a0) { 9 b0: 10 ; CHECK: asr{{.*}}:rnd 11 %v0 = alloca i32, align 4 12 store i32 %a0, i32* %v0, align 4 13 %v1 = load i32, i32* %v0, align 4 14 %v2 = ashr i32 %v1, 10 15 %v3 = add nsw i32 %v2, 1 16 %v4 = ashr i32 %v3, 1 17 ret i32 %v4 18 } 19 20 define i64 @f1(i64 %a0) { 21 b0: 22 ; CHECK: asr{{.*}}:rnd 23 %v0 = alloca i64, align 8 24 store i64 %a0, i64* %v0, align 8 25 %v1 = load i64, i64* %v0, align 8 26 %v2 = ashr i64 %v1, 17 27 %v3 = add nsw i64 %v2, 1 28 %v4 = ashr i64 %v3, 1 29 ret i64 %v4 30 } 31
