1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; CHECK-LABEL: t00 4 ; CHECK: and(q{{[0-3]}},q{{[0-3]}}) 5 define <64 x i8> @t00(<64 x i8> %a0, <64 x i8> %a1) #0 { 6 %q0 = trunc <64 x i8> %a0 to <64 x i1> 7 %q1 = trunc <64 x i8> %a1 to <64 x i1> 8 %q2 = and <64 x i1> %q0, %q1 9 %v0 = zext <64 x i1> %q2 to <64 x i8> 10 ret <64 x i8> %v0 11 } 12 13 ; CHECK-LABEL: t01 14 ; CHECK: or(q{{[0-3]}},q{{[0-3]}}) 15 define <64 x i8> @t01(<64 x i8> %a0, <64 x i8> %a1) #0 { 16 %q0 = trunc <64 x i8> %a0 to <64 x i1> 17 %q1 = trunc <64 x i8> %a1 to <64 x i1> 18 %q2 = or <64 x i1> %q0, %q1 19 %v0 = zext <64 x i1> %q2 to <64 x i8> 20 ret <64 x i8> %v0 21 } 22 23 ; CHECK-LABEL: t02 24 ; CHECK: xor(q{{[0-3]}},q{{[0-3]}}) 25 define <64 x i8> @t02(<64 x i8> %a0, <64 x i8> %a1) #0 { 26 %q0 = trunc <64 x i8> %a0 to <64 x i1> 27 %q1 = trunc <64 x i8> %a1 to <64 x i1> 28 %q2 = xor <64 x i1> %q0, %q1 29 %v0 = zext <64 x i1> %q2 to <64 x i8> 30 ret <64 x i8> %v0 31 } 32 33 ; CHECK-LABEL: t10 34 ; CHECK: and(q{{[0-3]}},q{{[0-3]}}) 35 define <32 x i16> @t10(<32 x i16> %a0, <32 x i16> %a1) #0 { 36 %q0 = trunc <32 x i16> %a0 to <32 x i1> 37 %q1 = trunc <32 x i16> %a1 to <32 x i1> 38 %q2 = and <32 x i1> %q0, %q1 39 %v0 = zext <32 x i1> %q2 to <32 x i16> 40 ret <32 x i16> %v0 41 } 42 43 ; CHECK-LABEL: t11 44 ; CHECK: or(q{{[0-3]}},q{{[0-3]}}) 45 define <32 x i16> @t11(<32 x i16> %a0, <32 x i16> %a1) #0 { 46 %q0 = trunc <32 x i16> %a0 to <32 x i1> 47 %q1 = trunc <32 x i16> %a1 to <32 x i1> 48 %q2 = or <32 x i1> %q0, %q1 49 %v0 = zext <32 x i1> %q2 to <32 x i16> 50 ret <32 x i16> %v0 51 } 52 53 ; CHECK-LABEL: t12 54 ; CHECK: xor(q{{[0-3]}},q{{[0-3]}}) 55 define <32 x i16> @t12(<32 x i16> %a0, <32 x i16> %a1) #0 { 56 %q0 = trunc <32 x i16> %a0 to <32 x i1> 57 %q1 = trunc <32 x i16> %a1 to <32 x i1> 58 %q2 = xor <32 x i1> %q0, %q1 59 %v0 = zext <32 x i1> %q2 to <32 x i16> 60 ret <32 x i16> %v0 61 } 62 63 ; CHECK-LABEL: t20 64 ; CHECK: and(q{{[0-3]}},q{{[0-3]}}) 65 define <16 x i32> @t20(<16 x i32> %a0, <16 x i32> %a1) #0 { 66 %q0 = trunc <16 x i32> %a0 to <16 x i1> 67 %q1 = trunc <16 x i32> %a1 to <16 x i1> 68 %q2 = and <16 x i1> %q0, %q1 69 %v0 = zext <16 x i1> %q2 to <16 x i32> 70 ret <16 x i32> %v0 71 } 72 73 ; CHECK-LABEL: t21 74 ; CHECK: or(q{{[0-3]}},q{{[0-3]}}) 75 define <16 x i32> @t21(<16 x i32> %a0, <16 x i32> %a1) #0 { 76 %q0 = trunc <16 x i32> %a0 to <16 x i1> 77 %q1 = trunc <16 x i32> %a1 to <16 x i1> 78 %q2 = or <16 x i1> %q0, %q1 79 %v0 = zext <16 x i1> %q2 to <16 x i32> 80 ret <16 x i32> %v0 81 } 82 83 ; CHECK-LABEL: t22 84 ; CHECK: xor(q{{[0-3]}},q{{[0-3]}}) 85 define <16 x i32> @t22(<16 x i32> %a0, <16 x i32> %a1) #0 { 86 %q0 = trunc <16 x i32> %a0 to <16 x i1> 87 %q1 = trunc <16 x i32> %a1 to <16 x i1> 88 %q2 = xor <16 x i1> %q0, %q1 89 %v0 = zext <16 x i1> %q2 to <16 x i32> 90 ret <16 x i32> %v0 91 } 92 93 attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 94
