1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; Check that extract-element is handled. 3 4 ; CHECK-LABEL: ext_00: 5 ; CHECK: r[[R000:[0-9]+]] = and(r0,#3) 6 ; CHECK: r[[R001:[0-9]+]] = vextract(v0,r0) 7 ; CHECK-DAG: r[[R002:[0-9]+]] = asl(r[[R000]],#3) 8 ; CHECK-DAG: r[[R003:[0-9]+]] = #8 9 ; CHECK: r0 = extractu(r[[R001]],r[[R003]]:[[R002]]) 10 define i8 @ext_00(<64 x i8> %a0, i32 %a1) #0 { 11 b2: 12 %v3 = extractelement <64 x i8> %a0, i32 %a1 13 ret i8 %v3 14 } 15 16 ; CHECK-LABEL: ext_10: 17 ; CHECK: r[[R100:[0-9]+]] = and(r0,#3) 18 ; CHECK: r[[R101:[0-9]+]] = vextract(v0,r0) 19 ; CHECK-DAG: r[[R102:[0-9]+]] = asl(r[[R100]],#3) 20 ; CHECK-DAG: r[[R103:[0-9]+]] = #8 21 ; CHECK: r0 = extractu(r[[R101]],r[[R103]]:[[R102]]) 22 define i8 @ext_10(<128 x i8> %a0, i32 %a1) #1 { 23 b2: 24 %v3 = extractelement <128 x i8> %a0, i32 %a1 25 ret i8 %v3 26 } 27 28 ; CHECK-LABEL: ext_01: 29 ; CHECK-DAG: r[[R010:[0-9]+]] = asl(r0,#1) 30 ; CHECK-DAG: r[[R011:[0-9]+]] = and(r0,#1) 31 ; CHECK-DAG: r[[R012:[0-9]+]] = #16 32 ; CHECK: r[[R013:[0-9]+]] = asl(r[[R011]],#4) 33 ; CHECK: r[[R014:[0-9]+]] = vextract(v0,r[[R010]]) 34 ; CHECK: r0 = extractu(r[[R014]],r[[R012]]:[[R013]]) 35 define i16 @ext_01(<32 x i16> %a0, i32 %a1) #0 { 36 b2: 37 %v3 = extractelement <32 x i16> %a0, i32 %a1 38 ret i16 %v3 39 } 40 41 ; CHECK-LABEL: ext_11: 42 ; CHECK-DAG: r[[R110:[0-9]+]] = asl(r0,#1) 43 ; CHECK-DAG: r[[R111:[0-9]+]] = and(r0,#1) 44 ; CHECK-DAG: r[[R112:[0-9]+]] = #16 45 ; CHECK: r[[R113:[0-9]+]] = asl(r[[R111]],#4) 46 ; CHECK: r[[R114:[0-9]+]] = vextract(v0,r[[R110]]) 47 ; CHECK: r0 = extractu(r[[R114]],r[[R112]]:[[R113]]) 48 define i16 @ext_11(<64 x i16> %a0, i32 %a1) #1 { 49 b2: 50 %v3 = extractelement <64 x i16> %a0, i32 %a1 51 ret i16 %v3 52 } 53 54 ; CHECK-LABEL: ext_02: 55 ; CHECK: [[R020:r[0-9]+]] = asl(r0,#2) 56 ; CHECK: r0 = vextract(v0,[[R020]]) 57 define i32 @ext_02(<16 x i32> %a0, i32 %a1) #0 { 58 b2: 59 %v3 = extractelement <16 x i32> %a0, i32 %a1 60 ret i32 %v3 61 } 62 63 ; CHECK-LABEL: ext_12: 64 ; CHECK: [[R120:r[0-9]+]] = asl(r0,#2) 65 ; CHECK: r0 = vextract(v0,[[R120]]) 66 define i32 @ext_12(<32 x i32> %a0, i32 %a1) #1 { 67 b2: 68 %v3 = extractelement <32 x i32> %a0, i32 %a1 69 ret i32 %v3 70 } 71 72 attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 73 attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } 74
