1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; Check that this compiles successfully. 4 ; CHECK: vsplat 5 6 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 7 target triple = "hexagon" 8 9 define void @fred() #0 { 10 b0: 11 %v1 = load <64 x i8>, <64 x i8>* undef, align 8 12 %v2 = zext <64 x i8> %v1 to <64 x i32> 13 %v3 = add nuw nsw <64 x i32> %v2, zeroinitializer 14 %v4 = icmp ugt <64 x i32> %v3, <i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254> 15 %v5 = zext <64 x i1> %v4 to <64 x i32> 16 %v6 = add nuw nsw <64 x i32> %v3, %v5 17 %v7 = trunc <64 x i32> %v6 to <64 x i8> 18 store <64 x i8> %v7, <64 x i8>* undef, align 8 19 ret void 20 } 21 22 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" } 23
