1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; CHECK-LABEL: f0: 4 ; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) 5 define <128 x i8> @f0() #0 { 6 ret <128 x i8> zeroinitializer 7 } 8 9 ; CHECK-LABEL: f1: 10 ; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) 11 define <64 x i16> @f1() #0 { 12 ret <64 x i16> zeroinitializer 13 } 14 15 ; CHECK-LABEL: f2: 16 ; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) 17 define <32 x i32> @f2() #0 { 18 ret <32 x i32> zeroinitializer 19 } 20 21 ; CHECK-LABEL: f3: 22 ; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) 23 define <256 x i8> @f3() #1 { 24 ret <256 x i8> zeroinitializer 25 } 26 27 ; CHECK-LABEL: f4: 28 ; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) 29 define <128 x i16> @f4() #1 { 30 ret <128 x i16> zeroinitializer 31 } 32 33 ; CHECK-LABEL: f5: 34 ; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) 35 define <64 x i32> @f5() #1 { 36 ret <64 x i32> zeroinitializer 37 } 38 39 attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 40 attributes #1 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } 41 42
