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      1 ; RUN: llc -march=hexagon < %s | FileCheck %s
      2 
      3 target triple = "hexagon"
      4 
      5 ; CHECK-LABEL: xh_sh
      6 ; CHECK: sath
      7 ; CHECK-NOT: sxth
      8 define i32 @xh_sh(i32 %x) local_unnamed_addr #0 {
      9 entry:
     10   %0 = tail call i32 @llvm.hexagon.A2.sath(i32 %x)
     11   %1 = tail call i32 @llvm.hexagon.A2.sxth(i32 %0)
     12   ret i32 %1
     13 }
     14 
     15 ; CHECK-LABEL: xb_sb
     16 ; CHECK: satb
     17 ; CHECK-NOT: sxtb
     18 define i32 @xb_sb(i32 %x) local_unnamed_addr #0 {
     19 entry:
     20   %0 = tail call i32 @llvm.hexagon.A2.satb(i32 %x)
     21   %1 = tail call i32 @llvm.hexagon.A2.sxtb(i32 %0)
     22   ret i32 %1
     23 }
     24 
     25 ; CHECK-LABEL: xuh_suh
     26 ; CHECK: satuh
     27 ; CHECK-NOT: zxth
     28 define i32 @xuh_suh(i32 %x) local_unnamed_addr #0 {
     29 entry:
     30   %0 = tail call i32 @llvm.hexagon.A2.satuh(i32 %x)
     31   %1 = tail call i32 @llvm.hexagon.A2.zxth(i32 %0)
     32   ret i32 %1
     33 }
     34 
     35 ; CHECK-LABEL: xub_sub
     36 ; CHECK: satub
     37 ; CHECK-NOT: zxtb
     38 define i32 @xub_sub(i32 %x) local_unnamed_addr #0 {
     39 entry:
     40   %0 = tail call i32 @llvm.hexagon.A2.satub(i32 %x)
     41   %1 = tail call i32 @llvm.hexagon.A2.zxtb(i32 %0)
     42   ret i32 %1
     43 }
     44 
     45 
     46 declare i32 @llvm.hexagon.A2.sxtb(i32) #1
     47 declare i32 @llvm.hexagon.A2.sxth(i32) #1
     48 declare i32 @llvm.hexagon.A2.zxtb(i32) #1
     49 declare i32 @llvm.hexagon.A2.zxth(i32) #1
     50 
     51 declare i32 @llvm.hexagon.A2.satb(i32) #1
     52 declare i32 @llvm.hexagon.A2.sath(i32) #1
     53 declare i32 @llvm.hexagon.A2.satub(i32) #1
     54 declare i32 @llvm.hexagon.A2.satuh(i32) #1
     55 
     56 attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
     57 attributes #1 = { nounwind readnone }
     58