1 ; RUN: llc -march=hexagon -hexbit-extract=0 < %s | FileCheck %s 2 3 ; Make sure we don't generate zxtb to transfer a predicate register into 4 ; a general purpose register. 5 6 ; CHECK: r0 = p0 7 ; CHECK-NOT: zxtb(p 8 ; CHECK-NOT: and(p 9 ; CHECK-NOT: extract(p 10 ; CHECK-NOT: extractu(p 11 12 target triple = "hexagon" 13 14 ; Function Attrs: nounwind 15 define i32 @fred() local_unnamed_addr #0 { 16 entry: 17 %0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef) 18 ret i32 %0 19 } 20 21 declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #1 22 23 attributes #0 = { nounwind "target-cpu"="hexagonv5" } 24 attributes #1 = { nounwind readnone } 25
