1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s 3 ; Testing bitreverse load intrinsics: 4 ; Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength); 5 ; Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength); 6 ; Q6_bitrev_load_update_H(inputLR, pDelay, nConvLength); 7 ; Q6_bitrev_load_update_UH(inputLR, pDelay, nConvLength); 8 ; Q6_bitrev_load_update_UB(inputLR, pDelay, nConvLength); 9 ; Q6_bitrev_load_update_B(inputLR, pDelay, nConvLength); 10 ; producing these instructions: 11 ; r3:2 = memd(r0++m0:brev) 12 ; r1 = memw(r0++m0:brev) 13 ; r1 = memh(r0++m0:brev) 14 ; r1 = memuh(r0++m0:brev) 15 ; r1 = memub(r0++m0:brev) 16 ; r1 = memb(r0++m0:brev) 17 18 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 19 target triple = "hexagon-unknown--elf" 20 21 ; CHECK: @call_brev_ldd 22 define i64* @call_brev_ldd(i64* %ptr, i64 %dst, i32 %mod) local_unnamed_addr #0 { 23 entry: 24 %0 = bitcast i64* %ptr to i8* 25 ; CHECK: = memd(r{{[0-9]*}}++m{{[0-1]}}:brev) 26 %1 = tail call { i64, i8* } @llvm.hexagon.L2.loadrd.pbr(i8* %0, i32 %mod) 27 %2 = extractvalue { i64, i8* } %1, 1 28 %3 = bitcast i8* %2 to i64* 29 ret i64* %3 30 } 31 32 ; CHECK: @call_brev_ldw 33 define i32* @call_brev_ldw(i32* %ptr, i32 %dst, i32 %mod) local_unnamed_addr #0 { 34 entry: 35 %0 = bitcast i32* %ptr to i8* 36 ; CHECK: = memw(r{{[0-9]*}}++m{{[0-1]}}:brev) 37 %1 = tail call { i32, i8* } @llvm.hexagon.L2.loadri.pbr(i8* %0, i32 %mod) 38 %2 = extractvalue { i32, i8* } %1, 1 39 %3 = bitcast i8* %2 to i32* 40 ret i32* %3 41 } 42 43 ; CHECK: @call_brev_ldh 44 define i16* @call_brev_ldh(i16* %ptr, i16 signext %dst, i32 %mod) local_unnamed_addr #0 { 45 entry: 46 %0 = bitcast i16* %ptr to i8* 47 ; CHECK: = memh(r{{[0-9]*}}++m{{[0-1]}}:brev) 48 %1 = tail call { i32, i8* } @llvm.hexagon.L2.loadrh.pbr(i8* %0, i32 %mod) 49 %2 = extractvalue { i32, i8* } %1, 1 50 %3 = bitcast i8* %2 to i16* 51 ret i16* %3 52 } 53 54 ; CHECK: @call_brev_lduh 55 define i16* @call_brev_lduh(i16* %ptr, i16 zeroext %dst, i32 %mod) local_unnamed_addr #0 { 56 entry: 57 %0 = bitcast i16* %ptr to i8* 58 ; CHECK: = memuh(r{{[0-9]*}}++m{{[0-1]}}:brev) 59 %1 = tail call { i32, i8* } @llvm.hexagon.L2.loadruh.pbr(i8* %0, i32 %mod) 60 %2 = extractvalue { i32, i8* } %1, 1 61 %3 = bitcast i8* %2 to i16* 62 ret i16* %3 63 } 64 65 ; CHECK: @call_brev_ldb 66 define i8* @call_brev_ldb(i8* %ptr, i8 signext %dst, i32 %mod) local_unnamed_addr #0 { 67 entry: 68 ; CHECK: = memb(r{{[0-9]*}}++m{{[0-1]}}:brev) 69 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrb.pbr(i8* %ptr, i32 %mod) 70 %1 = extractvalue { i32, i8* } %0, 1 71 ret i8* %1 72 } 73 74 ; Function Attrs: nounwind readonly 75 ; CHECK: @call_brev_ldub 76 define i8* @call_brev_ldub(i8* %ptr, i8 zeroext %dst, i32 %mod) local_unnamed_addr #0 { 77 entry: 78 ; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev) 79 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrub.pbr(i8* %ptr, i32 %mod) 80 %1 = extractvalue { i32, i8* } %0, 1 81 ret i8* %1 82 } 83 84 declare { i64, i8* } @llvm.hexagon.L2.loadrd.pbr(i8*, i32) #1 85 declare { i32, i8* } @llvm.hexagon.L2.loadri.pbr(i8*, i32) #1 86 declare { i32, i8* } @llvm.hexagon.L2.loadrh.pbr(i8*, i32) #1 87 declare { i32, i8* } @llvm.hexagon.L2.loadruh.pbr(i8*, i32) #1 88 declare { i32, i8* } @llvm.hexagon.L2.loadrb.pbr(i8*, i32) #1 89 declare { i32, i8* } @llvm.hexagon.L2.loadrub.pbr(i8*, i32) #1 90 91 attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" } 92 attributes #1 = { nounwind readonly } 93
