1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 ; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s 3 ; Test these 5 bitreverse store intrinsics: 4 ; Q6_bitrev_store_update_D(inputLR, pDelay, nConvLength); 5 ; Q6_bitrev_store_update_W(inputLR, pDelay, nConvLength); 6 ; Q6_bitrev_store_update_HL(inputLR, pDelay, nConvLength); 7 ; Q6_bitrev_store_update_HH(inputLR, pDelay, nConvLength); 8 ; Q6_bitrev_store_update_B(inputLR, pDelay, nConvLength); 9 ; producing these instructions: 10 ; memd(r0++m0:brev) = r1:0 11 ; memw(r0++m0:brev) = r0 12 ; memh(r0++m0:brev) = r3 13 ; memh(r0++m0:brev) = r3.h 14 ; memb(r0++m0:brev) = r3 15 16 ; ModuleID = 'brev_st.i' 17 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" 18 target triple = "hexagon" 19 20 define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 21 entry: 22 %conv = zext i16 %filtMemLen to i32 23 %shr2 = lshr i32 %conv, 1 24 %idxprom = sext i16 %filtMemIndex to i32 25 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 26 %0 = bitcast i16* %arrayidx to i8* 27 %sub = sub i32 13, %shr2 28 %shl = shl i32 1, %sub 29 ; CHECK: memd(r{{[0-9]*}}++m{{[0-1]}}:brev) 30 %1 = tail call i8* @llvm.hexagon.S2.storerd.pbr(i8* %0, i64 undef, i32 %shl) 31 ret i64 0 32 } 33 34 declare i8* @llvm.hexagon.S2.storerd.pbr(i8*, i64, i32) nounwind 35 36 define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 37 entry: 38 %conv = zext i16 %filtMemLen to i32 39 %shr1 = lshr i32 %conv, 1 40 %idxprom = sext i16 %filtMemIndex to i32 41 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 42 %0 = bitcast i16* %arrayidx to i8* 43 %sub = sub i32 14, %shr1 44 %shl = shl i32 1, %sub 45 ; CHECK: memw(r{{[0-9]*}}++m{{[0-1]}}:brev) 46 %1 = tail call i8* @llvm.hexagon.S2.storeri.pbr(i8* %0, i32 undef, i32 %shl) 47 ret i32 0 48 } 49 50 declare i8* @llvm.hexagon.S2.storeri.pbr(i8*, i32, i32) nounwind 51 52 define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 53 entry: 54 %conv = zext i16 %filtMemLen to i32 55 %shr2 = lshr i32 %conv, 1 56 %idxprom = sext i16 %filtMemIndex to i32 57 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 58 %0 = bitcast i16* %arrayidx to i8* 59 %sub = sub i32 15, %shr2 60 %shl = shl i32 1, %sub 61 ; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) 62 %1 = tail call i8* @llvm.hexagon.S2.storerh.pbr(i8* %0, i32 0, i32 %shl) 63 ret i16 0 64 } 65 66 declare i8* @llvm.hexagon.S2.storerh.pbr(i8*, i32, i32) nounwind 67 68 define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 69 entry: 70 %conv = zext i16 %filtMemLen to i32 71 %shr2 = lshr i32 %conv, 1 72 %idxprom = sext i16 %filtMemIndex to i32 73 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 74 %0 = bitcast i16* %arrayidx to i8* 75 %sub = sub i32 15, %shr2 76 %shl = shl i32 1, %sub 77 ; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) = r{{[0-9]*}}.h 78 %1 = tail call i8* @llvm.hexagon.S2.storerf.pbr(i8* %0, i32 0, i32 %shl) 79 ret i16 0 80 } 81 82 declare i8* @llvm.hexagon.S2.storerf.pbr(i8*, i32, i32) nounwind 83 84 define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { 85 entry: 86 %conv = zext i16 %filtMemLen to i32 87 %shr2 = lshr i32 %conv, 1 88 %idxprom = sext i16 %filtMemIndex to i32 89 %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom 90 %0 = bitcast i16* %arrayidx to i8* 91 %sub = sub nsw i32 16, %shr2 92 ; CHECK: memb(r{{[0-9]*}}++m{{[0-1]}}:brev) 93 %shl = shl i32 1, %sub 94 %1 = tail call i8* @llvm.hexagon.S2.storerb.pbr(i8* %0, i32 0, i32 %shl) 95 ret i8 0 96 } 97 98 declare i8* @llvm.hexagon.S2.storerb.pbr(i8*, i32, i32) nounwind 99 100 !0 = !{!"omnipotent char", !1} 101 !1 = !{!"Simple C/C++ TBAA"} 102 !2 = !{!"int", !0} 103 !3 = !{!"short", !0} 104
