1 ; RUN: llc -march=hexagon -O2 < %s 2 ; REQUIRES: asserts 3 4 define inreg <16 x i32> @f0(i32 %a0, <16 x i32>* nocapture %a1) #0 { 5 b0: 6 %v0 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a0) 7 %v1 = tail call <512 x i1> @llvm.hexagon.V6.pred.not(<512 x i1> %v0) 8 %v2 = icmp ult i32 %a0, 48 9 br i1 %v2, label %b1, label %b2 10 11 b1: ; preds = %b0 12 %v3 = add nuw nsw i32 %a0, 16 13 %v4 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v3) 14 %v5 = tail call <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1> %v4, <512 x i1> %v1) 15 br label %b2 16 17 b2: ; preds = %b1, %b0 18 %v6 = phi <512 x i1> [ %v5, %b1 ], [ %v1, %b0 ] 19 %v7 = bitcast <512 x i1> %v6 to <16 x i32> 20 %v8 = getelementptr inbounds <16 x i32>, <16 x i32>* %a1, i32 1 21 %v9 = load <16 x i32>, <16 x i32>* %v8, align 64 22 %v10 = getelementptr inbounds <16 x i32>, <16 x i32>* %a1, i32 2 23 %v11 = load <16 x i32>, <16 x i32>* %v10, align 64 24 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v6, <16 x i32> %v9, <16 x i32> %v11) 25 store <16 x i32> %v12, <16 x i32>* %a1, align 64 26 ret <16 x i32> %v7 27 } 28 29 ; Function Attrs: nounwind readnone 30 declare <512 x i1> @llvm.hexagon.V6.pred.not(<512 x i1>) #1 31 32 ; Function Attrs: nounwind readnone 33 declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1 34 35 ; Function Attrs: nounwind readnone 36 declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1 37 38 ; Function Attrs: nounwind readnone 39 declare <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1>, <16 x i32>, <16 x i32>) #1 40 41 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 42 attributes #1 = { nounwind readnone } 43
