1 ; RUN: llc -march=hexagon -O3 < %s | FileCheck %s 2 ; we really just want to be sure this compilation does not abort. 3 ; CHECK: vadd 4 5 target triple = "hexagon" 6 7 @g0 = private unnamed_addr constant [39 x i8] c"\0AnumTrainingSet =%d numFeatures = %d\0A\00", align 1 8 9 ; Function Attrs: nounwind 10 declare i32 @f0(i8* nocapture readonly, ...) #0 11 12 ; Function Attrs: nounwind 13 define void @f1(i16* nocapture readnone %a0, i16 signext %a1, i16 signext %a2, i16* nocapture readnone %a3, i16* nocapture readnone %a4, i16* nocapture %a5, i16 signext %a6, i16 signext %a7) #0 { 14 b0: 15 %v0 = sext i16 %a1 to i32 16 %v1 = sext i16 %a2 to i32 17 %v2 = tail call i32 (i8*, ...) @f0(i8* getelementptr inbounds ([39 x i8], [39 x i8]* @g0, i32 0, i32 0), i32 %v0, i32 %v1) #2 18 %v3 = tail call <32 x i32> @llvm.hexagon.V6.vd0.128B() 19 br label %b1 20 21 b1: ; preds = %b18, %b0 22 %v4 = phi i32 [ 0, %b0 ], [ %v57, %b18 ] 23 %v5 = phi <32 x i32> [ %v3, %b0 ], [ %v56, %b18 ] 24 %v6 = icmp slt i32 %v4, %v1 25 br i1 %v6, label %b2, label %b3 26 27 b2: ; preds = %b1 28 %v7 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 29 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v5, <32 x i32> %v7) 30 br label %b3 31 32 b3: ; preds = %b2, %b1 33 %v9 = phi <32 x i32> [ %v8, %b2 ], [ %v5, %b1 ] 34 %v10 = add nuw nsw i32 %v4, 1 35 %v11 = icmp slt i32 %v10, %v1 36 br i1 %v11, label %b5, label %b6 37 38 b4: ; preds = %b18 39 %v12 = sext i16 %a6 to i32 40 %v13 = tail call double @f3(double 1.000000e+00, i32 %v12) #2 41 %v14 = fptosi double %v13 to i32 42 %v15 = mul nsw i32 %v0, 2 43 %v16 = sitofp i32 %v15 to double 44 %v17 = tail call double @f3(double 1.000000e+00, i32 %v12) #2 45 %v18 = fmul double %v16, %v17 46 %v19 = fptosi double %v18 to i32 47 %v20 = tail call i32 @f2(i32 %v14, i32 %v19, i16 signext %a6) #2 48 %v21 = extractelement <32 x i32> %v56, i32 0 49 %v22 = mul nsw i32 %v20, %v21 50 %v23 = trunc i32 %v22 to i16 51 store i16 %v23, i16* %a5, align 2, !tbaa !0 52 ret void 53 54 b5: ; preds = %b3 55 %v24 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 56 %v25 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v9, <32 x i32> %v24) 57 br label %b6 58 59 b6: ; preds = %b5, %b3 60 %v26 = phi <32 x i32> [ %v25, %b5 ], [ %v9, %b3 ] 61 %v27 = add nsw i32 %v4, 2 62 %v28 = icmp slt i32 %v27, %v1 63 br i1 %v28, label %b7, label %b8 64 65 b7: ; preds = %b6 66 %v29 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 67 %v30 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v26, <32 x i32> %v29) 68 br label %b8 69 70 b8: ; preds = %b7, %b6 71 %v31 = phi <32 x i32> [ %v30, %b7 ], [ %v26, %b6 ] 72 %v32 = add nsw i32 %v4, 3 73 %v33 = icmp slt i32 %v32, %v1 74 br i1 %v33, label %b9, label %b10 75 76 b9: ; preds = %b8 77 %v34 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 78 %v35 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v31, <32 x i32> %v34) 79 br label %b10 80 81 b10: ; preds = %b9, %b8 82 %v36 = phi <32 x i32> [ %v35, %b9 ], [ %v31, %b8 ] 83 %v37 = add nsw i32 %v4, 4 84 %v38 = icmp slt i32 %v37, %v1 85 br i1 %v38, label %b11, label %b12 86 87 b11: ; preds = %b10 88 %v39 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 89 %v40 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v36, <32 x i32> %v39) 90 br label %b12 91 92 b12: ; preds = %b11, %b10 93 %v41 = phi <32 x i32> [ %v40, %b11 ], [ %v36, %b10 ] 94 %v42 = add nsw i32 %v4, 5 95 %v43 = icmp slt i32 %v42, %v1 96 br i1 %v43, label %b13, label %b14 97 98 b13: ; preds = %b12 99 %v44 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 100 %v45 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v41, <32 x i32> %v44) 101 br label %b14 102 103 b14: ; preds = %b13, %b12 104 %v46 = phi <32 x i32> [ %v45, %b13 ], [ %v41, %b12 ] 105 %v47 = add nsw i32 %v4, 6 106 %v48 = icmp slt i32 %v47, %v1 107 br i1 %v48, label %b15, label %b16 108 109 b15: ; preds = %b14 110 %v49 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 111 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v46, <32 x i32> %v49) 112 br label %b16 113 114 b16: ; preds = %b15, %b14 115 %v51 = phi <32 x i32> [ %v50, %b15 ], [ %v46, %b14 ] 116 %v52 = add nsw i32 %v4, 7 117 %v53 = icmp slt i32 %v52, %v1 118 br i1 %v53, label %b17, label %b18 119 120 b17: ; preds = %b16 121 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> undef, i32 16) 122 %v55 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v51, <32 x i32> %v54) 123 br label %b18 124 125 b18: ; preds = %b17, %b16 126 %v56 = phi <32 x i32> [ %v55, %b17 ], [ %v51, %b16 ] 127 %v57 = add nsw i32 %v4, 8 128 %v58 = icmp eq i32 %v57, 64 129 br i1 %v58, label %b4, label %b1 130 } 131 132 ; Function Attrs: nounwind readnone 133 declare <32 x i32> @llvm.hexagon.V6.vd0.128B() #1 134 135 ; Function Attrs: nounwind readnone 136 declare <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32>, i32) #1 137 138 ; Function Attrs: nounwind readnone 139 declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1 140 141 declare i32 @f2(i32, i32, i16 signext) #0 142 143 declare double @f3(double, i32) 144 145 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } 146 attributes #1 = { nounwind readnone } 147 attributes #2 = { nounwind } 148 149 !0 = !{!1, !1, i64 0} 150 !1 = !{!"short", !2, i64 0} 151 !2 = !{!"omnipotent char", !3, i64 0} 152 !3 = !{!"Simple C/C++ TBAA"} 153
