1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; CHECK-LABEL: test1 4 ; CHECK: m[[REG1:([0-1])]] = r0 5 ; CHECK: cs[[REG1]] = r1 6 ; CHECK: = memub(r1++#4:circ(m[[REG1]]) 7 define zeroext i8 @test1(i32 %mod, i8* %start) local_unnamed_addr #0 { 8 entry: 9 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrub.pci(i8* %start, i32 4, i32 %mod, i8* %start) 10 %1 = extractvalue { i32, i8* } %0, 0 11 %conv = trunc i32 %1 to i8 12 ret i8 %conv 13 } 14 15 declare { i32, i8* } @llvm.hexagon.L2.loadrub.pci(i8*, i32, i32, i8* nocapture) #1 16 17 ; CHECK-LABEL: test2 18 ; CHECK: m[[REG2:([0-1])]] = r0 19 ; CHECK: cs[[REG2]] = r1 20 ; CHECK: = memb(r1++#4:circ(m[[REG2]]) 21 define zeroext i8 @test2(i32 %mod, i8* %start) local_unnamed_addr #0 { 22 entry: 23 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrb.pci(i8* %start, i32 4, i32 %mod, i8* %start) 24 %1 = extractvalue { i32, i8* } %0, 0 25 %conv = trunc i32 %1 to i8 26 ret i8 %conv 27 } 28 29 declare { i32, i8* } @llvm.hexagon.L2.loadrb.pci(i8*, i32, i32, i8* nocapture) #1 30 31 ; CHECK-LABEL: test3 32 ; CHECK: m[[REG3:([0-1])]] = r0 33 ; CHECK: cs[[REG3]] = r1 34 ; CHECK: = memuh(r1++#4:circ(m[[REG3]]) 35 define zeroext i16 @test3(i32 %mod, i8* %start) local_unnamed_addr #0 { 36 entry: 37 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadruh.pci(i8* %start, i32 4, i32 %mod, i8* %start) 38 %1 = extractvalue { i32, i8* } %0, 0 39 %conv = trunc i32 %1 to i16 40 ret i16 %conv 41 } 42 43 declare { i32, i8* } @llvm.hexagon.L2.loadruh.pci(i8*, i32, i32, i8* nocapture) #1 44 45 ; CHECK-LABEL: test4 46 ; CHECK: m[[REG4:([0-1])]] = r0 47 ; CHECK: cs[[REG4]] = r1 48 ; CHECK: = memh(r1++#4:circ(m[[REG4]]) 49 define signext i16 @test4(i32 %mod, i8* %start) local_unnamed_addr #0 { 50 entry: 51 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrh.pci(i8* %start, i32 4, i32 %mod, i8* %start) 52 %1 = extractvalue { i32, i8* } %0, 0 53 %conv = trunc i32 %1 to i16 54 ret i16 %conv 55 } 56 57 declare { i32, i8* } @llvm.hexagon.L2.loadrh.pci(i8*, i32, i32, i8* nocapture) #1 58 59 ; CHECK-LABEL: test5 60 ; CHECK: m[[REG5:([0-1])]] = r0 61 ; CHECK: cs[[REG5]] = r1 62 ; CHECK: = memw(r1++#4:circ(m[[REG5]]) 63 define i32 @test5(i32 %mod, i8* %start) local_unnamed_addr #0 { 64 entry: 65 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadri.pci(i8* %start, i32 4, i32 %mod, i8* %start) 66 %1 = extractvalue { i32, i8* } %0, 0 67 ret i32 %1 68 } 69 70 declare { i32, i8* } @llvm.hexagon.L2.loadri.pci(i8*, i32, i32, i8* nocapture) #1 71 72 ; CHECK-LABEL: test6 73 ; CHECK: m[[REG6:([0-1])]] = r0 74 ; CHECK: cs[[REG6]] = r1 75 ; CHECK: = memd(r1++#8:circ(m[[REG6]]) 76 define i64 @test6(i32 %mod, i8* %start) local_unnamed_addr #0 { 77 entry: 78 %0 = tail call { i64, i8* } @llvm.hexagon.L2.loadrd.pci(i8* %start, i32 8, i32 %mod, i8* %start) 79 %1 = extractvalue { i64, i8* } %0, 0 80 ret i64 %1 81 } 82 83 declare { i64, i8* } @llvm.hexagon.L2.loadrd.pci(i8*, i32, i32, i8* nocapture) #1 84 85 ; CHECK-LABEL: test7 86 ; CHECK: m[[REG7:([0-1])]] = r0 87 ; CHECK: cs[[REG7]] = r1 88 ; CHECK: = memub(r1++I:circ(m[[REG7]]) 89 define zeroext i8 @test7(i32 %mod, i8* %start) local_unnamed_addr #0 { 90 entry: 91 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrub.pcr(i8* %start, i32 %mod, i8* %start) 92 %1 = extractvalue { i32, i8* } %0, 0 93 %conv = trunc i32 %1 to i8 94 ret i8 %conv 95 } 96 97 declare { i32, i8* } @llvm.hexagon.L2.loadrub.pcr(i8*, i32, i8* nocapture) #1 98 99 ; CHECK-LABEL: test8 100 ; CHECK: m[[REG8:([0-1])]] = r0 101 ; CHECK: cs[[REG8]] = r1 102 ; CHECK: = memb(r1++I:circ(m[[REG8]]) 103 define zeroext i8 @test8(i32 %mod, i8* %start) local_unnamed_addr #0 { 104 entry: 105 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrb.pcr(i8* %start, i32 %mod, i8* %start) 106 %1 = extractvalue { i32, i8* } %0, 0 107 %conv = trunc i32 %1 to i8 108 ret i8 %conv 109 } 110 111 declare { i32, i8* } @llvm.hexagon.L2.loadrb.pcr(i8*, i32, i8* nocapture) #1 112 113 ; CHECK-LABEL: test9 114 ; CHECK: m[[REG9:([0-1])]] = r0 115 ; CHECK: cs[[REG9]] = r1 116 ; CHECK: = memuh(r1++I:circ(m[[REG9]]) 117 define zeroext i16 @test9(i32 %mod, i8* %start) local_unnamed_addr #0 { 118 entry: 119 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadruh.pcr(i8* %start, i32 %mod, i8* %start) 120 %1 = extractvalue { i32, i8* } %0, 0 121 %conv = trunc i32 %1 to i16 122 ret i16 %conv 123 } 124 125 declare { i32, i8* } @llvm.hexagon.L2.loadruh.pcr(i8*, i32, i8* nocapture) #1 126 127 ; CHECK-LABEL: test10 128 ; CHECK: m[[REG10:([0-1])]] = r0 129 ; CHECK: cs[[REG10]] = r1 130 ; CHECK: = memh(r1++I:circ(m[[REG10]]) 131 define signext i16 @test10(i32 %mod, i8* %start) local_unnamed_addr #0 { 132 entry: 133 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrh.pcr(i8* %start, i32 %mod, i8* %start) 134 %1 = extractvalue { i32, i8* } %0, 0 135 %conv = trunc i32 %1 to i16 136 ret i16 %conv 137 } 138 139 declare { i32, i8* } @llvm.hexagon.L2.loadrh.pcr(i8*, i32, i8* nocapture) #1 140 141 ; CHECK-LABEL: test11 142 ; CHECK: m[[REG11:([0-1])]] = r0 143 ; CHECK: cs[[REG11]] = r1 144 ; CHECK: = memw(r1++I:circ(m[[REG11]]) 145 define i32 @test11(i32 %mod, i8* %start) local_unnamed_addr #0 { 146 entry: 147 %0 = tail call { i32, i8* } @llvm.hexagon.L2.loadri.pcr(i8* %start, i32 %mod, i8* %start) 148 %1 = extractvalue { i32, i8* } %0, 0 149 ret i32 %1 150 } 151 152 declare { i32, i8* } @llvm.hexagon.L2.loadri.pcr(i8*, i32, i8* nocapture) #1 153 154 ; CHECK-LABEL: test12 155 ; CHECK: m[[REG12:([0-1])]] = r0 156 ; CHECK: cs[[REG12]] = r1 157 ; CHECK: = memd(r1++I:circ(m[[REG12]]) 158 define i64 @test12(i32 %mod, i8* %start) local_unnamed_addr #0 { 159 entry: 160 %0 = tail call { i64, i8* } @llvm.hexagon.L2.loadrd.pcr(i8* %start, i32 %mod, i8* %start) 161 %1 = extractvalue { i64, i8* } %0, 0 162 ret i64 %1 163 } 164 165 declare { i64, i8* } @llvm.hexagon.L2.loadrd.pcr(i8*, i32, i8* nocapture) #1 166 167 ; CHECK-LABEL: test13 168 ; CHECK: m[[REG13:([0-1])]] = r0 169 ; CHECK: cs[[REG13]] = r1 170 ; CHECK: memb(r1++#4:circ(m[[REG13]])) = 171 define void @test13(i32 %mod, i8* %start, i8 zeroext %v) local_unnamed_addr #0 { 172 entry: 173 %conv = zext i8 %v to i32 174 %0 = tail call i8* @llvm.hexagon.S2.storerb.pci(i8* %start, i32 4, i32 %mod, i32 %conv, i8* %start) 175 ret void 176 } 177 178 declare i8* @llvm.hexagon.S2.storerb.pci(i8*, i32, i32, i32, i8* nocapture) #1 179 180 ; CHECK-LABEL: test14 181 ; CHECK: m[[REG14:([0-1])]] = r0 182 ; CHECK: cs[[REG14]] = r1 183 ; CHECK: memh(r1++#4:circ(m[[REG14]])) = 184 define void @test14(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 { 185 entry: 186 %conv = sext i16 %v to i32 187 %0 = tail call i8* @llvm.hexagon.S2.storerh.pci(i8* %start, i32 4, i32 %mod, i32 %conv, i8* %start) 188 ret void 189 } 190 191 declare i8* @llvm.hexagon.S2.storerh.pci(i8*, i32, i32, i32, i8* nocapture) #1 192 193 ; CHECK-LABEL: test15 194 ; CHECK: m[[REG15:([0-1])]] = r0 195 ; CHECK: cs[[REG15]] = r1 196 ; CHECK: memh(r1++#4:circ(m[[REG15]])) = r{{[0-9]+}}.h 197 define void @test15(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 { 198 entry: 199 %conv = sext i16 %v to i32 200 %0 = tail call i8* @llvm.hexagon.S2.storerf.pci(i8* %start, i32 4, i32 %mod, i32 %conv, i8* %start) 201 ret void 202 } 203 204 declare i8* @llvm.hexagon.S2.storerf.pci(i8*, i32, i32, i32, i8* nocapture) #1 205 206 ; CHECK-LABEL: test16 207 ; CHECK: m[[REG16:([0-1])]] = r0 208 ; CHECK: cs[[REG16]] = r1 209 ; CHECK: memw(r1++#4:circ(m[[REG16]])) = 210 define void @test16(i32 %mod, i8* %start, i32 %v) local_unnamed_addr #0 { 211 entry: 212 %0 = tail call i8* @llvm.hexagon.S2.storeri.pci(i8* %start, i32 4, i32 %mod, i32 %v, i8* %start) 213 ret void 214 } 215 216 declare i8* @llvm.hexagon.S2.storeri.pci(i8*, i32, i32, i32, i8* nocapture) #1 217 218 ; CHECK-LABEL: test17 219 ; CHECK: m[[REG17:([0-1])]] = r0 220 ; CHECK: cs[[REG17]] = r1 221 ; CHECK: memd(r1++#8:circ(m[[REG17]])) = 222 define void @test17(i32 %mod, i8* %start, i64 %v) local_unnamed_addr #0 { 223 entry: 224 %0 = tail call i8* @llvm.hexagon.S2.storerd.pci(i8* %start, i32 8, i32 %mod, i64 %v, i8* %start) 225 ret void 226 } 227 228 declare i8* @llvm.hexagon.S2.storerd.pci(i8*, i32, i32, i64, i8* nocapture) #1 229 230 ; CHECK-LABEL: test18 231 ; CHECK: m[[REG18:([0-1])]] = r0 232 ; CHECK: cs[[REG18]] = r1 233 ; CHECK: memb(r1++I:circ(m[[REG18]])) = 234 define void @test18(i32 %mod, i8* %start, i8 zeroext %v) local_unnamed_addr #0 { 235 entry: 236 %conv = zext i8 %v to i32 237 %0 = tail call i8* @llvm.hexagon.S2.storerb.pcr(i8* %start, i32 %mod, i32 %conv, i8* %start) 238 ret void 239 } 240 241 declare i8* @llvm.hexagon.S2.storerb.pcr(i8*, i32, i32, i8* nocapture) #1 242 243 ; CHECK-LABEL: test19 244 ; CHECK: m[[REG19:([0-1])]] = r0 245 ; CHECK: cs[[REG19]] = r1 246 ; CHECK: memh(r1++I:circ(m[[REG19]])) = 247 define void @test19(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 { 248 entry: 249 %conv = sext i16 %v to i32 250 %0 = tail call i8* @llvm.hexagon.S2.storerh.pcr(i8* %start, i32 %mod, i32 %conv, i8* %start) 251 ret void 252 } 253 254 declare i8* @llvm.hexagon.S2.storerh.pcr(i8*, i32, i32, i8* nocapture) #1 255 256 ; CHECK-LABEL: test20 257 ; CHECK: m[[REG20:([0-1])]] = r0 258 ; CHECK: cs[[REG20]] = r1 259 ; CHECK: memh(r1++I:circ(m[[REG20]])) = r{{[0-9]+}}.h 260 define void @test20(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 { 261 entry: 262 %conv = sext i16 %v to i32 263 %0 = tail call i8* @llvm.hexagon.S2.storerf.pcr(i8* %start, i32 %mod, i32 %conv, i8* %start) 264 ret void 265 } 266 267 declare i8* @llvm.hexagon.S2.storerf.pcr(i8*, i32, i32, i8* nocapture) #1 268 269 ; CHECK-LABEL: test21 270 ; CHECK: m[[REG21:([0-1])]] = r0 271 ; CHECK: cs[[REG21]] = r1 272 ; CHECK: memw(r1++I:circ(m[[REG21]])) = 273 define void @test21(i32 %mod, i8* %start, i32 %v) local_unnamed_addr #0 { 274 entry: 275 %0 = tail call i8* @llvm.hexagon.S2.storeri.pcr(i8* %start, i32 %mod, i32 %v, i8* %start) 276 ret void 277 } 278 279 declare i8* @llvm.hexagon.S2.storeri.pcr(i8*, i32, i32, i8* nocapture) #1 280 281 ; CHECK-LABEL: test22 282 ; CHECK: m[[REG22:([0-1])]] = r0 283 ; CHECK: cs[[REG22]] = r1 284 ; CHECK: memd(r1++I:circ(m[[REG1]])) = 285 define void @test22(i32 %mod, i8* %start, i64 %v) local_unnamed_addr #0 { 286 entry: 287 %0 = tail call i8* @llvm.hexagon.S2.storerd.pcr(i8* %start, i32 %mod, i64 %v, i8* %start) 288 ret void 289 } 290 291 declare i8* @llvm.hexagon.S2.storerd.pcr(i8*, i32, i64, i8* nocapture) #1 292 293 attributes #0 = { nounwind "target-cpu"="hexagonv60" } 294 attributes #1 = { argmemonly nounwind } 295
