1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s 2 ; r2 = round(r1:0):sat 3 ; r3 = cmpyiwh(r1:0, r2):<<1:rnd:sat 4 ; r0 = cmpyiwh(r1:0, r2*):<<1:rnd:sat 5 6 ; CHECK: round(r{{[0-9]*}}:{{[0-9]*}}):sat 7 ; CHECK: cmpyiwh(r{{[0-9]*}}:{{[0-9]*}},r{{[0-9]*}}):<<1:rnd:sat 8 ; CHECK: cmpyrwh(r{{[0-9]*}}:{{[0-9]*}},r{{[0-9]*}}*):<<1:rnd:sat 9 ; CHECK: cmpyiwh(r{{[0-9]*}}:{{[0-9]*}},r{{[0-9]*}}*):<<1:rnd:sat 10 11 target triple = "hexagon" 12 13 @g0 = global i32 0, align 4 14 @g1 = global i32 0, align 4 15 @g2 = global i32 0, align 4 16 17 ; Function Attrs: nounwind 18 define i32 @f0() #0 { 19 b0: 20 %v0 = alloca i32, align 4 21 %v1 = alloca i32, align 4 22 store i32 0, i32* %v0 23 store i32 0, i32* %v1, align 4 24 %v2 = call i32 @llvm.hexagon.A2.roundsat(i64 1) 25 store i32 %v2, i32* @g1, align 4 26 %v3 = call i32 @llvm.hexagon.M4.cmpyi.wh(i64 -2147483648, i32 -2147483648) 27 store i32 %v3, i32* @g0, align 4 28 %v4 = call i32 @llvm.hexagon.M4.cmpyr.whc(i64 2147483647, i32 2147483647) 29 store i32 %v4, i32* @g2, align 4 30 %v5 = call i32 @llvm.hexagon.M4.cmpyi.whc(i64 -2147483648, i32 -2147483648) 31 ret i32 %v5 32 } 33 34 ; Function Attrs: nounwind readnone 35 declare i32 @llvm.hexagon.A2.roundsat(i64) #1 36 37 ; Function Attrs: nounwind readnone 38 declare i32 @llvm.hexagon.M4.cmpyi.wh(i64, i32) #1 39 40 ; Function Attrs: nounwind readnone 41 declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32) #1 42 43 ; Function Attrs: nounwind readnone 44 declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32) #1 45 46 attributes #0 = { nounwind "target-cpu"="hexagonv55" } 47 attributes #1 = { nounwind readnone } 48
