1 ; RUN: llc -march=hexagon -mcpu=hexagonv55 -filetype=obj -o /dev/null 2 ; REQUIRES: asserts 3 ; There should be no output (nothing on stderr). 4 5 ; Due to a bug in converting a dot-new branch into a dot-old one, opcodes 6 ; with branch prediction bits were selected even if the architecture did 7 ; not support them. On V55-, the dot-old branch opcodes are J2_jumpt and 8 ; J2_jumpf (and a pair of J2_jumpr*), whereas J2_jumptpt could have been 9 ; a result of the conversion to dot-old. This would fail a verification 10 ; check in the MC code emitter, so make sure it does not happen. 11 12 target triple = "hexagon" 13 14 define void @fred(i16* nocapture %a0, i16* nocapture %a1, i16* nocapture %a2, i16 signext %a3, i16* %a4, i16 signext %a5, i16 signext %a6, i16 signext %a7, i32 %a8, i16 signext %a9, i16 signext %a10) local_unnamed_addr #0 { 15 b11: 16 %v12 = sext i16 %a5 to i32 17 %v13 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v12) 18 %v14 = tail call i32 @llvm.hexagon.A2.sxth(i32 2) 19 %v15 = tail call i32 @llvm.hexagon.A2.sxth(i32 undef) 20 %v16 = tail call i32 @llvm.hexagon.A2.sath(i32 undef) 21 %v17 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v16) 22 %v18 = tail call i32 @llvm.hexagon.A2.aslh(i32 undef) 23 %v19 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v18, i32 %v14) 24 %v20 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v19) 25 %v21 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v20) 26 %v22 = tail call i32 @llvm.hexagon.A2.sub(i32 %v17, i32 %v21) 27 %v23 = tail call i32 @llvm.hexagon.A2.sath(i32 %v22) 28 %v24 = select i1 undef, i32 undef, i32 %v23 29 %v25 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v24) 30 %v26 = tail call i32 @llvm.hexagon.A2.sub(i32 %v13, i32 %v25) 31 %v27 = tail call i32 @llvm.hexagon.A2.sath(i32 %v26) 32 %v28 = tail call i32 @llvm.hexagon.A2.sxth(i32 %v27) 33 %v29 = tail call i32 @llvm.hexagon.A2.sub(i32 %v28, i32 %v14) 34 %v30 = tail call i32 @llvm.hexagon.A2.sath(i32 %v29) 35 %v31 = shl i32 %v30, 16 36 %v32 = icmp sgt i32 undef, %v31 37 %v33 = select i1 %v32, i32 %v30, i32 undef 38 %v34 = trunc i32 %v33 to i16 39 %v35 = trunc i32 %v24 to i16 40 call void @foo(i16* nonnull undef, i32* nonnull undef, i16* %a4, i16 signext %v35, i16 signext %v34, i16 signext 2) #4 41 %v36 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v18, i32 undef) 42 %v37 = call i32 @llvm.hexagon.A2.asrh(i32 %v36) 43 %v38 = call i32 @llvm.hexagon.A2.sub(i32 %v13, i32 undef) 44 %v39 = call i32 @llvm.hexagon.A2.sath(i32 %v38) 45 %v40 = call i32 @llvm.hexagon.A2.sxth(i32 %v39) 46 %v41 = call i32 @llvm.hexagon.A2.sub(i32 %v40, i32 %v14) 47 %v42 = call i32 @llvm.hexagon.A2.sath(i32 %v41) 48 %v43 = select i1 undef, i32 %v42, i32 %v37 49 %v44 = trunc i32 %v43 to i16 50 call void @foo(i16* nonnull undef, i32* nonnull undef, i16* %a4, i16 signext undef, i16 signext %v44, i16 signext 2) #4 51 %v45 = call i32 @llvm.hexagon.A2.sath(i32 undef) 52 %v46 = select i1 undef, i32 undef, i32 %v45 53 %v47 = trunc i32 %v46 to i16 54 call void @foo(i16* nonnull undef, i32* nonnull undef, i16* %a4, i16 signext %v47, i16 signext undef, i16 signext 2) #4 55 %v48 = call i32 @llvm.hexagon.A2.sub(i32 undef, i32 %v15) 56 %v49 = call i32 @llvm.hexagon.A2.sath(i32 %v48) 57 %v50 = trunc i32 %v49 to i16 58 store i16 %v50, i16* undef, align 2 59 store i16 %a3, i16* %a0, align 2 60 %v51 = sext i16 %a10 to i32 61 %v52 = call i32 @llvm.hexagon.A2.sxth(i32 %v51) 62 %v53 = call i32 @llvm.hexagon.A2.add(i32 undef, i32 %v52) 63 %v54 = call i32 @llvm.hexagon.A2.sath(i32 %v53) 64 %v55 = trunc i32 %v54 to i16 65 store i16 %v55, i16* %a1, align 2 66 store i16 %a7, i16* %a2, align 2 67 %v56 = sext i16 %a9 to i32 68 %v57 = call i32 @llvm.hexagon.A2.sxth(i32 %v56) 69 br i1 undef, label %b58, label %b62 70 71 b58: ; preds = %b11 72 %v59 = call i32 @llvm.hexagon.A2.add(i32 %v57, i32 %v52) 73 %v60 = call i32 @llvm.hexagon.A2.sath(i32 %v59) 74 %v61 = trunc i32 %v60 to i16 75 store i16 %v61, i16* %a1, align 2 76 br label %b63 77 78 b62: ; preds = %b11 79 br label %b63 80 81 b63: ; preds = %b62, %b58 82 %v64 = phi i16 [ undef, %b58 ], [ %a9, %b62 ] 83 %v65 = icmp slt i16 undef, %v64 84 br i1 %v65, label %b66, label %b67 85 86 b66: ; preds = %b63 87 br i1 undef, label %b67, label %b68 88 89 b67: ; preds = %b66, %b63 90 store i16 0, i16* %a2, align 2 91 br label %b68 92 93 b68: ; preds = %b67, %b66 94 ret void 95 } 96 97 declare i32 @llvm.hexagon.A2.sath(i32) #2 98 declare i32 @llvm.hexagon.A2.add(i32, i32) #2 99 declare i32 @llvm.hexagon.A2.sxth(i32) #2 100 declare i32 @llvm.hexagon.A2.sub(i32, i32) #2 101 declare i32 @llvm.hexagon.A2.asrh(i32) #2 102 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2 103 declare i32 @llvm.hexagon.A2.aslh(i32) #2 104 declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3 105 106 attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } 107 attributes #1 = { argmemonly nounwind } 108 attributes #2 = { nounwind readnone } 109 attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } 110 attributes #4 = { nounwind optsize } 111
